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author | Keir Fraser <keir@xen.org> | 2010-10-29 10:40:14 +0100 |
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committer | Keir Fraser <keir@xen.org> | 2010-10-29 10:40:14 +0100 |
commit | fd1291a826e17108d7c7f20c887847daba451ef4 (patch) | |
tree | 963f0da4548bc87d110ff0a4982f1b14f913be29 /xen/include/asm-x86/hvm/vcpu.h | |
parent | 9dbd1007376011d99e6af1dd703c2cc437e7fda0 (diff) | |
download | xen-fd1291a826e17108d7c7f20c887847daba451ef4.tar.gz xen-fd1291a826e17108d7c7f20c887847daba451ef4.tar.bz2 xen-fd1291a826e17108d7c7f20c887847daba451ef4.zip |
X86: Prefer TSC-deadline timer in Xen
The new TSC Deadline Timer offers system software a low overhead
per-logical-thread deadline timer in TSC units.
The timer is implemented via a new architectural 64-bit register,
IA32_TSC_DEADLINE_MSR. Reads and writes of this MSR occur in program
order, but are non-serializing.
The support for this feature is indicated by
CPUID.01H:ECX.TSC_Deadline[bit 24] =3D 1 as documented in the Intel
Architecture Software Developer's Manual.
The LOCAL APIC on new processors has a mode where its underlying
hardware timer can now be accessed via the non-serializing
IA32_TSC_DEADLINE_MSR in TSC tick units.
If this mode is present, prefer it over the traditional LAPIC timer
mode. KERN_DEBUG dmesg will print "TSC deadline timer enabled" when
TDT is used.
Bootparam "tdt=off" is available to revert to LAPIC timer mode.
This patch is based on original work by Len Brown for Linux kernel.
cc: Len Brown <len.brown@intel.com>
Signed-off-by: Wei Gang <gang.wei@intel.com>
Signed-off-by: Keir Fraser <keir@xen.org>
Diffstat (limited to 'xen/include/asm-x86/hvm/vcpu.h')
0 files changed, 0 insertions, 0 deletions