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authorkaf24@scramble.cl.cam.ac.uk <kaf24@scramble.cl.cam.ac.uk>2004-11-21 20:41:00 +0000
committerkaf24@scramble.cl.cam.ac.uk <kaf24@scramble.cl.cam.ac.uk>2004-11-21 20:41:00 +0000
commitc81cf54c19d633c7840e626b1c0ef91e60935795 (patch)
tree3edb2f13409863f3e16fffa3600534a1fbf5faea /xen/include/asm-x86/hardirq.h
parent9b7223024d973757421cd6b037f47f64bc41e59d (diff)
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bitkeeper revision 1.1159.183.1 (41a0fd5c_SO-Z8P4u52CN53Q0eDzqg)
Clean up cacheline-alignment attribute usage. Also add an extra byte to the TSS I/O bitmap as required by the arch manual.
Diffstat (limited to 'xen/include/asm-x86/hardirq.h')
-rw-r--r--xen/include/asm-x86/hardirq.h3
1 files changed, 1 insertions, 2 deletions
diff --git a/xen/include/asm-x86/hardirq.h b/xen/include/asm-x86/hardirq.h
index 811415e98a..576efd3c7c 100644
--- a/xen/include/asm-x86/hardirq.h
+++ b/xen/include/asm-x86/hardirq.h
@@ -4,13 +4,12 @@
#include <xen/config.h>
#include <xen/cache.h>
-/* assembly code in softirq.h is sensitive to the offsets of these fields */
typedef struct {
unsigned int __softirq_pending;
unsigned int __local_irq_count;
unsigned int __nmi_count;
unsigned long idle_timestamp;
-} ____cacheline_aligned irq_cpustat_t;
+} __cacheline_aligned irq_cpustat_t;
#include <xen/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */