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| author | Ian Campbell <ian.campbell@citrix.com> | 2013-07-17 12:19:28 +0100 |
|---|---|---|
| committer | Ian Campbell <ian.campbell@citrix.com> | 2013-07-29 16:54:48 +0100 |
| commit | 225ece46211328723a79f13152cb904c0b0f38b2 (patch) | |
| tree | ac903393dfee900d81a2eb7d35d4d4fff116827c /xen/include/asm-arm/arm32 | |
| parent | cda3deadd4d67ae9d9e8a694774bd3f6cb0c3943 (diff) | |
| download | xen-225ece46211328723a79f13152cb904c0b0f38b2.tar.gz xen-225ece46211328723a79f13152cb904c0b0f38b2.tar.bz2 xen-225ece46211328723a79f13152cb904c0b0f38b2.zip | |
xen: arm: remove unnecessary cache flush in write_pte
On a ARMv7/v8 SMP system the MMU is coherent
Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Tim Deegan <tim@xen.org>
[ ijc -- dropped the associated dsb too ]
Diffstat (limited to 'xen/include/asm-arm/arm32')
| -rw-r--r-- | xen/include/asm-arm/arm32/page.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h index 38bcffde6d..cf12a89ae6 100644 --- a/xen/include/asm-arm/arm32/page.h +++ b/xen/include/asm-arm/arm32/page.h @@ -16,10 +16,6 @@ static inline void write_pte(lpae_t *p, lpae_t pte) /* Safely write the entry (STRD is atomic on CPUs that support LPAE) */ "strd %0, %H0, [%1];" "dsb;" - /* Push this cacheline to the PoC so the rest of the system sees it. */ - STORE_CP32(1, DCCMVAC) - /* Ensure that the data flush is completed before proceeding */ - "dsb;" : : "r" (pte.bits), "r" (p) : "memory"); } |