x86_emulate: Emulate RDTSC instruction.

Signed-off-by: Keir Fraser <keir.fraser@citrix.com>

1 files changed, 24 insertions, 2 deletions

diff --git a/xen/arch/x86/x86_emulate.c b/xen/arch/x86/x86_emulate.c
index 8343b33fcd..d19f3ddde0 100644
--- a/xen/arch/x86/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate.c
@@ -191,7 +191,7 @@ static uint8_t twobyte_table[256] = {
     /* 0x28 - 0x2F */
     0, 0, 0, 0, 0, 0, 0, 0,
     /* 0x30 - 0x37 */
-    ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0,
+    ImplicitOps, ImplicitOps, ImplicitOps, 0, 0, 0, 0, 0,
     /* 0x38 - 0x3F */
     0, 0, 0, 0, 0, 0, 0, 0,
     /* 0x40 - 0x47 */
@@ -271,6 +271,13 @@ struct operand {
     };
 };
 
+/* MSRs. */
+#define MSR_TSC   0x10
+
+/* Control register flags. */
+#define CR0_PE    (1<<0)
+#define CR4_TSD   (1<<2)
+
 /* EFLAGS bit definitions. */
 #define EFLG_VIP  (1<<20)
 #define EFLG_VIF  (1<<19)
@@ -739,7 +746,7 @@ in_realmode(
         return 0;
 
     rc = ops->read_cr(0, &cr0, ctxt);
-    return (!rc && !(cr0 & 1));
+    return (!rc && !(cr0 & CR0_PE));
 }
 
 static int
@@ -2860,6 +2867,21 @@ x86_emulate(
         break;
     }
 
+    case 0x31: /* rdtsc */ {
+        unsigned long cr4;
+        uint64_t val;
+        fail_if(ops->read_cr == NULL);
+        if ( (rc = ops->read_cr(4, &cr4, ctxt)) )
+            goto done;
+        generate_exception_if((cr4 & CR4_TSD) && !mode_ring0(), EXC_GP);
+        fail_if(ops->read_msr == NULL);
+        if ( (rc = ops->read_msr(MSR_TSC, &val, ctxt)) != 0 )
+            goto done;
+        _regs.edx = (uint32_t)(val >> 32);
+        _regs.eax = (uint32_t)(val >>  0);
+        break;
+    }
+
     case 0x32: /* rdmsr */ {
         uint64_t val;
         generate_exception_if(!mode_ring0(), EXC_GP);