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| author | Liu, Jinsong <jinsong.liu@intel.com> | 2011-12-01 12:22:43 +0100 |
|---|---|---|
| committer | Liu, Jinsong <jinsong.liu@intel.com> | 2011-12-01 12:22:43 +0100 |
| commit | b0933946291cba0f47f288ad6eb22a3c69321091 (patch) | |
| tree | 57ad1ceb1191c8499d105554c351be2826a9852f /xen/arch/x86/traps.c | |
| parent | 500161db50e3430026b5374462c1bdac00257abe (diff) | |
| download | xen-b0933946291cba0f47f288ad6eb22a3c69321091.tar.gz xen-b0933946291cba0f47f288ad6eb22a3c69321091.tar.bz2 xen-b0933946291cba0f47f288ad6eb22a3c69321091.zip | |
X86: Disable PCID/INVPCID for dom0
PCID (Process-context identifier) is a facility by which a logical
processor may cache information for multiple linear-address spaces.
INVPCID is an new instruction to invalidate TLB. Refer latest Intel SDM
http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html
We disable PCID/INVPCID for dom0 and pv. Exposing them into dom0 and pv
may result in performance regression, and it would trigger GP or UD
depending on whether platform suppport INVPCID or not.
This patch disables PCID/INVPCID for dom0.
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
Committed-by: Jan Beulich <jbeulich@suse.com>
Diffstat (limited to 'xen/arch/x86/traps.c')
| -rw-r--r-- | xen/arch/x86/traps.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 03dc7c3501..7f38ddce6b 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -841,6 +841,7 @@ static void pv_cpuid(struct cpu_user_regs *regs) __clear_bit(X86_FEATURE_CX16 % 32, &c); __clear_bit(X86_FEATURE_XTPR % 32, &c); __clear_bit(X86_FEATURE_PDCM % 32, &c); + __clear_bit(X86_FEATURE_PCID % 32, &c); __clear_bit(X86_FEATURE_DCA % 32, &c); if ( !xsave_enabled(current) ) { |