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| author | Keir Fraser <keir.fraser@citrix.com> | 2010-06-24 21:56:03 +0100 |
|---|---|---|
| committer | Keir Fraser <keir.fraser@citrix.com> | 2010-06-24 21:56:03 +0100 |
| commit | be9a6b532389149d4b0480f2a647e971b5ec5bda (patch) | |
| tree | 64ca46b86f3574b66a4f9794bd7d9b3153be5b6a /xen/arch/x86/nmi.c | |
| parent | beb367d559f07dd19648c1aa4a54ee79e404059e (diff) | |
| download | xen-be9a6b532389149d4b0480f2a647e971b5ec5bda.tar.gz xen-be9a6b532389149d4b0480f2a647e971b5ec5bda.tar.bz2 xen-be9a6b532389149d4b0480f2a647e971b5ec5bda.zip | |
x86: use rdmsrl/wrmsrl
Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
Diffstat (limited to 'xen/arch/x86/nmi.c')
| -rw-r--r-- | xen/arch/x86/nmi.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/xen/arch/x86/nmi.c b/xen/arch/x86/nmi.c index d6fd625d01..f3155e8b76 100644 --- a/xen/arch/x86/nmi.c +++ b/xen/arch/x86/nmi.c @@ -276,9 +276,9 @@ static void __pminit setup_p6_watchdog(unsigned counter) static int __pminit setup_p4_watchdog(void) { - unsigned int misc_enable, dummy; + uint64_t misc_enable; - rdmsr(MSR_IA32_MISC_ENABLE, misc_enable, dummy); + rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); if (!(misc_enable & MSR_IA32_MISC_ENABLE_PERF_AVAIL)) return 0; @@ -304,11 +304,11 @@ static int __pminit setup_p4_watchdog(void) clear_msr_range(MSR_P4_BPU_CCCR0, 18); clear_msr_range(MSR_P4_BPU_PERFCTR0, 18); - wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0); - wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0); + wrmsrl(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0); + wrmsrl(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE); write_watchdog_counter("P4_IQ_COUNTER0"); apic_write(APIC_LVTPC, APIC_DM_NMI); - wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0); + wrmsrl(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val); return 1; } @@ -442,7 +442,7 @@ void nmi_watchdog_tick(struct cpu_user_regs * regs) * - LVTPC is masked on interrupt and must be * unmasked by the LVTPC handler. */ - wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0); + wrmsrl(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val); apic_write(APIC_LVTPC, APIC_DM_NMI); } else if ( nmi_perfctr_msr == MSR_P6_PERFCTR0 ) |