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authorKeir Fraser <keir.fraser@citrix.com>2008-10-20 15:11:19 +0100
committerKeir Fraser <keir.fraser@citrix.com>2008-10-20 15:11:19 +0100
commit4fe64c10cb285a270ba9a7b630ed33b009f0c633 (patch)
treea6fb5de4a07bf28dd3fadcac7d72b5ab1375a854 /xen/arch/x86/nmi.c
parent942da08c6c66aa8ebd0db4d7cbe0b06426bc6c53 (diff)
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NMI watchdog: don't try to run too slow.
The way MSR writes of performance counters works means that Intel CPUs running faster than about 2.1GHz can't set the NMI timer to 1Hz. Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com>
Diffstat (limited to 'xen/arch/x86/nmi.c')
-rw-r--r--xen/arch/x86/nmi.c13
1 files changed, 10 insertions, 3 deletions
diff --git a/xen/arch/x86/nmi.c b/xen/arch/x86/nmi.c
index 47e53b2a2a..edc323cd38 100644
--- a/xen/arch/x86/nmi.c
+++ b/xen/arch/x86/nmi.c
@@ -122,10 +122,17 @@ int __init check_nmi_watchdog (void)
printk("\n");
- /* now that we know it works we can reduce NMI frequency to
- something more reasonable; makes a difference in some configs */
+ /*
+ * Now that we know it works we can reduce NMI frequency to
+ * something more reasonable; makes a difference in some configs.
+ * There's a limit to how slow we can go because writing the perfctr
+ * MSRs only sets the low 32 bits, with the top 8 bits sign-extended
+ * from those, so it's not possible to set up a delay larger than
+ * 2^31 cycles and smaller than (2^40 - 2^31) cycles.
+ * (Intel SDM, section 18.22.2)
+ */
if ( nmi_watchdog == NMI_LOCAL_APIC )
- nmi_hz = 1;
+ nmi_hz = max(1ul, cpu_khz >> 20);
return 0;
}