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| author | kaf24@firebug.cl.cam.ac.uk <kaf24@firebug.cl.cam.ac.uk> | 2006-04-04 15:00:41 +0100 |
|---|---|---|
| committer | kaf24@firebug.cl.cam.ac.uk <kaf24@firebug.cl.cam.ac.uk> | 2006-04-04 15:00:41 +0100 |
| commit | c8a220e4f7659f1824ee6c4e426aed745468f59c (patch) | |
| tree | aa58d86d34256b911ec7220df5dd9d93fc98f082 /xen/arch/x86/mpparse.c | |
| parent | 295b4af4a1d4869f6b9990c4312a4397bf9429d3 (diff) | |
| download | xen-c8a220e4f7659f1824ee6c4e426aed745468f59c.tar.gz xen-c8a220e4f7659f1824ee6c4e426aed745468f59c.tar.bz2 xen-c8a220e4f7659f1824ee6c4e426aed745468f59c.zip | |
Simplify the Xen genapic code. Many genapic hooks have been
replaced with unconditional static 'sane' implementations.
Functions relating to interrupt/IPI delivery have been
grouped into two sets: physical delivery and logical-flat
delivery. All subarchitectures use physical delivery except
the basic default subarchitecture.
The main behavioural changes are:
1. Summit no longer uses logical-clustered delivery mode
2. Physical mode no longer makes any pretence to set the
LDR sanely. We never deliver interrupts in logical mode
so this really should not matter.
3. Sanity checking of phys_cpu_present_map is enabled
for all subarchitectures. Really we should have a sane
set of APIC IDs in the system, as we rely on them for
physical delivery mode.
4. We enable 'bigsmp' mode on any system with more than
eight CPUs. The previous xAPIC check was unnecessary,
since our bigsmp mode uses physical delivery, not
logical-clustered.
This all obviously needs testing on some big systems.
Signed-off-by: Keir Fraser <keir@xensource.com>
Diffstat (limited to 'xen/arch/x86/mpparse.c')
| -rw-r--r-- | xen/arch/x86/mpparse.c | 27 |
1 files changed, 14 insertions, 13 deletions
diff --git a/xen/arch/x86/mpparse.c b/xen/arch/x86/mpparse.c index 2df055f33a..3a53d91fd8 100644 --- a/xen/arch/x86/mpparse.c +++ b/xen/arch/x86/mpparse.c @@ -35,7 +35,7 @@ /* Have we found an MP table */ int smp_found_config; -unsigned int __initdata maxcpus = NR_CPUS; +unsigned int __devinitdata maxcpus = NR_CPUS; #ifdef CONFIG_HOTPLUG_CPU #define CPU_HOTPLUG_ENABLED (1) @@ -226,16 +226,11 @@ static void __devinit MP_processor_info (struct mpc_config_processor *m) num_processors++; if (CPU_HOTPLUG_ENABLED || (num_processors > 8)) { - switch (boot_cpu_data.x86_vendor) { - case X86_VENDOR_INTEL: - if (!APIC_XAPIC(ver)) { - def_to_bigsmp = 0; - break; - } - /* If P4 and above fall through */ - case X86_VENDOR_AMD: - def_to_bigsmp = 1; - } + /* + * No need for processor or APIC checks: physical delivery + * (bigsmp) mode should always work. + */ + def_to_bigsmp = 1; } bios_cpu_apicid[num_processors - 1] = m->mpc_apicid; } @@ -916,6 +911,7 @@ void __init mp_register_ioapic ( u32 gsi_base) { int idx = 0; + int tmpid; if (nr_ioapics >= MAX_IO_APICS) { printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded " @@ -936,9 +932,14 @@ void __init mp_register_ioapic ( set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 < 15)) - mp_ioapics[idx].mpc_apicid = io_apic_get_unique_id(idx, id); + tmpid = io_apic_get_unique_id(idx, id); else - mp_ioapics[idx].mpc_apicid = id; + tmpid = id; + if (tmpid == -1) { + nr_ioapics--; + return; + } + mp_ioapics[idx].mpc_apicid = tmpid; mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx); /* |