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authorkaf24@firebug.cl.cam.ac.uk <kaf24@firebug.cl.cam.ac.uk>2006-02-06 16:51:06 +0100
committerkaf24@firebug.cl.cam.ac.uk <kaf24@firebug.cl.cam.ac.uk>2006-02-06 16:51:06 +0100
commit695affde7f098ea1a842944a1e9bb5f7ce8ea695 (patch)
treed3a8094964cc434480c6efe6636bb85f99854602 /xen/arch/x86/mpparse.c
parent326db4216a1bf4c2ffa3e8cde3dfb84628848b69 (diff)
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No C1-Clock Ramp disabling on AMD processors. The tiny drift
caused by the ramping changes should not cause TSCs to become noticeably out of sync on Xen systems. Signed-off-by: Keir Fraser <keir@xensource.com>
Diffstat (limited to 'xen/arch/x86/mpparse.c')
-rw-r--r--xen/arch/x86/mpparse.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/xen/arch/x86/mpparse.c b/xen/arch/x86/mpparse.c
index f4c61b4d33..999315ab27 100644
--- a/xen/arch/x86/mpparse.c
+++ b/xen/arch/x86/mpparse.c
@@ -730,11 +730,6 @@ void __init get_smp_config (void)
*/
}
-int __init mp_get_num_processors(void)
-{
- return num_processors;
-}
-
static int __init smp_scan_config (unsigned long base, unsigned long length)
{
unsigned int *bp = maddr_to_virt(base);