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| author | Yang Zhang <yang.z.zhang@Intel.com> | 2013-08-06 17:22:35 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2013-08-06 17:22:35 +0200 |
| commit | e1ab5c77b44b7bd835a2c032fa4963b36545fdb3 (patch) | |
| tree | 69a4dd9d1b28b3dc86ed0b977a334a0c70927467 /xen/arch/x86/mm | |
| parent | c58d9f2f4844c2ce8859a8d0f26a54cd058eb51f (diff) | |
| download | xen-e1ab5c77b44b7bd835a2c032fa4963b36545fdb3.tar.gz xen-e1ab5c77b44b7bd835a2c032fa4963b36545fdb3.tar.bz2 xen-e1ab5c77b44b7bd835a2c032fa4963b36545fdb3.zip | |
Nested VMX: Flush TLBs and Caches if paging mode changed
According to SDM, if paging mode is changed, then whole TLBs and caches will
be flushed. This is missed in nested handle logic. Also this fixed the issue
that 64 bits windows cannot boot up on top of L1 kvm.
Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com>
Acked-by: Keir Fraser <keir@xen.org>
Diffstat (limited to 'xen/arch/x86/mm')
| -rw-r--r-- | xen/arch/x86/mm/paging.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/xen/arch/x86/mm/paging.c b/xen/arch/x86/mm/paging.c index cd08b2a204..4ba7669a34 100644 --- a/xen/arch/x86/mm/paging.c +++ b/xen/arch/x86/mm/paging.c @@ -709,6 +709,7 @@ void paging_update_nestedmode(struct vcpu *v) else /* TODO: shadow-on-shadow */ v->arch.paging.nestedmode = NULL; + hvm_asid_flush_vcpu(v); } void paging_write_p2m_entry(struct p2m_domain *p2m, unsigned long gfn, |