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| author | Yang Zhang <yang.z.zhang@Intel.com> | 2013-08-22 10:52:05 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2013-08-22 10:52:05 +0200 |
| commit | 375a1035002fb257087756a86e6caeda649fc0f1 (patch) | |
| tree | de93f2578b2c6b631051c0d18810e16950da0e80 /xen/arch/x86/hvm/vmx | |
| parent | b35d0a26983843c092bfa353fd6b9aa8c3bf4886 (diff) | |
| download | xen-375a1035002fb257087756a86e6caeda649fc0f1.tar.gz xen-375a1035002fb257087756a86e6caeda649fc0f1.tar.bz2 xen-375a1035002fb257087756a86e6caeda649fc0f1.zip | |
Nested VMX: Clear APIC-v control bit in vmcs02
There is no vAPIC-v support, so mask APIC-v control bit when
constructing vmcs02.
Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com>
Acked-by: "Dong, Eddie" <eddie.dong@intel.com>
Diffstat (limited to 'xen/arch/x86/hvm/vmx')
| -rw-r--r-- | xen/arch/x86/hvm/vmx/vvmx.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index 5dfbc54d94..0dc567a972 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -613,8 +613,15 @@ void nvmx_update_secondary_exec_control(struct vcpu *v, u32 shadow_cntrl; struct nestedvcpu *nvcpu = &vcpu_nestedhvm(v); struct nestedvmx *nvmx = &vcpu_2_nvmx(v); + u32 apicv_bit = SECONDARY_EXEC_APIC_REGISTER_VIRT | + SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY; + host_cntrl &= ~apicv_bit; shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx, SECONDARY_VM_EXEC_CONTROL); + + /* No vAPIC-v support, so it shouldn't be set in vmcs12. */ + ASSERT(!(shadow_cntrl & apicv_bit)); + nvmx->ept.enabled = !!(shadow_cntrl & SECONDARY_EXEC_ENABLE_EPT); shadow_cntrl |= host_cntrl; __vmwrite(SECONDARY_VM_EXEC_CONTROL, shadow_cntrl); @@ -625,7 +632,12 @@ static void nvmx_update_pin_control(struct vcpu *v, unsigned long host_cntrl) u32 shadow_cntrl; struct nestedvcpu *nvcpu = &vcpu_nestedhvm(v); + host_cntrl &= ~PIN_BASED_POSTED_INTERRUPT; shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx, PIN_BASED_VM_EXEC_CONTROL); + + /* No vAPIC-v support, so it shouldn't be set in vmcs12. */ + ASSERT(!(shadow_cntrl & PIN_BASED_POSTED_INTERRUPT)); + shadow_cntrl |= host_cntrl; __vmwrite(PIN_BASED_VM_EXEC_CONTROL, shadow_cntrl); } |