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| author | Yongan Liu <Liuyongan@huawei.com> | 2012-01-05 09:29:59 +0100 |
|---|---|---|
| committer | Yongan Liu <Liuyongan@huawei.com> | 2012-01-05 09:29:59 +0100 |
| commit | b4799791c1e88341688142408051e65867bcdf82 (patch) | |
| tree | 2ab5b878c79421032d3c270d0cc105294ca2f0f3 /xen/arch/x86/hvm/vlapic.c | |
| parent | a33389c34e9dd9e4877dd96c5b189fc9d6230ff7 (diff) | |
| download | xen-b4799791c1e88341688142408051e65867bcdf82.tar.gz xen-b4799791c1e88341688142408051e65867bcdf82.tar.bz2 xen-b4799791c1e88341688142408051e65867bcdf82.zip | |
x86/vIRQ: IRR and TMR race condition bug fix
In vlapic_set_irq, we set the IRR register before the TMR. And the IRR
might be serviced before setting TMR, and even worse EOI might occur
before TMR setting, in which case the vioapic_update_EOI won't be
called, and further prevent all the subsequent interrupt injecting.
Reorder setting the TMR and IRR will solve the problem.
Besides, KVM has fixed a similar bug in:
http://markmail.org/search/?q=APIC_TMR#query:APIC_TMR+page:1+mid:rphs4f7lkxjlldne+state:results
Signed-off-by: Yongan Liu<Liuyongan@huawei.com>
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Committed-by: Jan Beulich <jbeulich@suse.com>
Diffstat (limited to 'xen/arch/x86/hvm/vlapic.c')
| -rw-r--r-- | xen/arch/x86/hvm/vlapic.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c index 8b05f1adc3..b4142875ef 100644 --- a/xen/arch/x86/hvm/vlapic.c +++ b/xen/arch/x86/hvm/vlapic.c @@ -142,14 +142,11 @@ static int vlapic_find_highest_irr(struct vlapic *vlapic) int vlapic_set_irq(struct vlapic *vlapic, uint8_t vec, uint8_t trig) { - int ret; - - ret = !vlapic_test_and_set_irr(vec, vlapic); if ( trig ) vlapic_set_vector(vec, &vlapic->regs->data[APIC_TMR]); /* We may need to wake up target vcpu, besides set pending bit here */ - return ret; + return !vlapic_test_and_set_irr(vec, vlapic); } static int vlapic_find_highest_isr(struct vlapic *vlapic) |