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author | Zhenguo Wang <wangzhenguo@huawei.com> | 2013-06-11 09:45:55 +0200 |
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committer | Jan Beulich <jbeulich@suse.com> | 2013-06-11 09:45:55 +0200 |
commit | 6859874b61d5ddaf5289e72ed2b2157739b72ca5 (patch) | |
tree | 802d566b6482c49e4b75992908424feb25e835aa /xen/arch/x86/hvm/vlapic.c | |
parent | 44434f3c5e998e10b23939755751abb344d80d73 (diff) | |
download | xen-6859874b61d5ddaf5289e72ed2b2157739b72ca5.tar.gz xen-6859874b61d5ddaf5289e72ed2b2157739b72ca5.tar.bz2 xen-6859874b61d5ddaf5289e72ed2b2157739b72ca5.zip |
x86/HVM: fix x2APIC APIC_ID read emulation
APIC and x2APIC have different format for APIC_ID register. Need
translation.
Signed-off-by: Zhenguo Wang <wangzhenguo@huawei.com>
Signed-off-by: Xiaowei Yang <xiaowei.yang@huawei.com>
Convert code to use switch(), fixing coding style issue at once, and
use GET_xAPIC_ID() on the value read instead of VLAPIC_ID() (reading
the field again).
In the course of this also properly reject both read and writes on the
non-existing MSR corresponding to APIC_ICR2.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Keir Fraser <keir@xen.org>
Diffstat (limited to 'xen/arch/x86/hvm/vlapic.c')
-rw-r--r-- | xen/arch/x86/hvm/vlapic.c | 23 |
1 files changed, 20 insertions, 3 deletions
diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c index 8c6a7e234d..7dea8fbc93 100644 --- a/xen/arch/x86/hvm/vlapic.c +++ b/xen/arch/x86/hvm/vlapic.c @@ -582,8 +582,19 @@ int hvm_x2apic_msr_read(struct vcpu *v, unsigned int msr, uint64_t *msr_content) return 1; vlapic_read_aligned(vlapic, offset, &low); - if ( offset == APIC_ICR ) + switch ( offset ) + { + case APIC_ID: + low = GET_xAPIC_ID(low); + break; + + case APIC_ICR: vlapic_read_aligned(vlapic, APIC_ICR2, &high); + break; + + case APIC_ICR2: + return 1; + } *msr_content = (((uint64_t)high) << 32) | low; return 0; @@ -837,11 +848,17 @@ int hvm_x2apic_msr_write(struct vcpu *v, unsigned int msr, uint64_t msr_content) if ( !vlapic_x2apic_mode(vlapic) ) return X86EMUL_UNHANDLEABLE; - if ( offset == APIC_ICR ) + switch ( offset ) { - int rc = vlapic_reg_write(v, APIC_ICR2, (uint32_t)(msr_content >> 32)); + int rc; + + case APIC_ICR: + rc = vlapic_reg_write(v, APIC_ICR2, (uint32_t)(msr_content >> 32)); if ( rc ) return rc; + + case APIC_ICR2: + return X86EMUL_UNHANDLEABLE; } return vlapic_reg_write(v, offset, (uint32_t)msr_content); |