Simplify the Xen genapic code. Many genapic hooks have been

replaced with unconditional static 'sane' implementations.
Functions relating to interrupt/IPI delivery have been
grouped into two sets: physical delivery and logical-flat
delivery. All subarchitectures use physical delivery except
the basic default subarchitecture.

The main behavioural changes are:
 1. Summit no longer uses logical-clustered delivery mode
 2. Physical mode no longer makes any pretence to set the
    LDR sanely. We never deliver interrupts in logical mode
    so this really should not matter.
 3. Sanity checking of phys_cpu_present_map is enabled
    for all subarchitectures. Really we should have a sane
    set of APIC IDs in the system, as we rely on them for
    physical delivery mode.
 4. We enable 'bigsmp' mode on any system with more than
    eight CPUs. The previous xAPIC check was unnecessary,
    since our bigsmp mode uses physical delivery, not
    logical-clustered.

This all obviously needs testing on some big systems.

Signed-off-by: Keir Fraser <keir@xensource.com>

6 files changed, 73 insertions, 16 deletions

diff --git a/xen/arch/x86/genapic/Makefile b/xen/arch/x86/genapic/Makefile
index 4220d8f7fe..ea51ead30a 100644
--- a/xen/arch/x86/genapic/Makefile
+++ b/xen/arch/x86/genapic/Makefile
@@ -2,6 +2,7 @@ include $(BASEDIR)/Rules.mk
 
 obj-y += bigsmp.o
 obj-y += default.o
+obj-y += delivery.o
 obj-y += es7000.o
 obj-y += es7000plat.o
 obj-y += probe.o
diff --git a/xen/arch/x86/genapic/bigsmp.c b/xen/arch/x86/genapic/bigsmp.c
index 4338e5765e..ae714a8282 100644
--- a/xen/arch/x86/genapic/bigsmp.c
+++ b/xen/arch/x86/genapic/bigsmp.c
@@ -1,7 +1,3 @@
-/* 
- * APIC driver for "bigsmp" XAPIC machines with more than 8 virtual CPUs.
- * Drives the local APIC in "clustered mode".
- */
 #include <xen/config.h>
 #include <xen/cpumask.h>
 #include <asm/current.h>
@@ -13,8 +9,6 @@
 #include <xen/smp.h>
 #include <xen/init.h>
 #include <xen/dmi.h>
-#include <asm/mach_ipi.h>
-#include <asm/mach-bigsmp/mach_apic.h>
 #include <asm/mach-default/mach_mpparse.h>
 
 static int dmi_bigsmp; /* can be set by dmi scanners */
@@ -52,5 +46,5 @@ static __init int probe_bigsmp(void)
 
 struct genapic apic_bigsmp = {
 	APIC_INIT("bigsmp", probe_bigsmp),
-	.send_ipi_mask = send_IPI_mask_sequence
+	GENAPIC_PHYS
 };
diff --git a/xen/arch/x86/genapic/default.c b/xen/arch/x86/genapic/default.c
index a7403922bb..0e766937fc 100644
--- a/xen/arch/x86/genapic/default.c
+++ b/xen/arch/x86/genapic/default.c
@@ -12,8 +12,6 @@
 #include <xen/string.h>
 #include <xen/smp.h>
 #include <xen/init.h>
-#include <asm/mach_ipi.h>
-#include <asm/mach-default/mach_apic.h>
 #include <asm/mach-default/mach_mpparse.h>
 
 /* should be called last. */
@@ -24,5 +22,5 @@ static __init int probe_default(void)
 
 struct genapic apic_default = {
 	APIC_INIT("default", probe_default),
-	.send_ipi_mask = send_IPI_mask_bitmask
+	GENAPIC_FLAT
 };
diff --git a/xen/arch/x86/genapic/delivery.c b/xen/arch/x86/genapic/delivery.c
new file mode 100644
index 0000000000..e343220f73
--- /dev/null
+++ b/xen/arch/x86/genapic/delivery.c
@@ -0,0 +1,68 @@
+#include <xen/config.h>
+#include <xen/irq.h>
+#include <xen/sched.h>
+#include <asm/current.h>
+#include <asm/smp.h>
+#include <asm/hardirq.h>
+#include <mach_apic.h>
+
+
+/*
+ * LOGICAL FLAT DELIVERY MODE (multicast via bitmask to <= 8 logical APIC IDs).
+ */
+
+void init_apic_ldr_flat(void)
+{
+	unsigned long val;
+
+	apic_write_around(APIC_DFR, APIC_DFR_FLAT);
+	val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
+	val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
+	apic_write_around(APIC_LDR, val);
+}
+
+void clustered_apic_check_flat(void)
+{
+	printk("Enabling APIC mode:  Flat.  Using %d I/O APICs\n", nr_ioapics);
+}
+
+cpumask_t target_cpus_flat(void)
+{
+	return cpu_online_map;
+} 
+
+unsigned int cpu_mask_to_apicid_flat(cpumask_t cpumask)
+{
+	return cpus_addr(cpumask)[0];
+}
+
+
+/*
+ * PHYSICAL DELIVERY MODE (unicast to physical APIC IDs).
+ */
+
+void init_apic_ldr_phys(void)
+{
+	unsigned long val;
+	apic_write_around(APIC_DFR, APIC_DFR_FLAT);
+	/* A dummy logical ID should be fine. We only deliver in phys mode. */
+	val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
+	apic_write_around(APIC_LDR, val);
+}
+
+void clustered_apic_check_phys(void)
+{
+	printk("Enabling APIC mode:  Phys.  Using %d I/O APICs\n", nr_ioapics);
+}
+
+cpumask_t target_cpus_phys(void)
+{
+	/* IRQs will get bound more accurately later. */
+	return cpumask_of_cpu(0);
+}
+
+unsigned int cpu_mask_to_apicid_phys(cpumask_t cpumask)
+{
+	/* As we are using single CPU as destination, pick only one CPU here */
+	return cpu_physical_id(first_cpu(cpumask));
+}
diff --git a/xen/arch/x86/genapic/es7000.c b/xen/arch/x86/genapic/es7000.c
index 37c959bf4c..09228f7dea 100644
--- a/xen/arch/x86/genapic/es7000.c
+++ b/xen/arch/x86/genapic/es7000.c
@@ -13,8 +13,6 @@
 #include <xen/string.h>
 #include <xen/smp.h>
 #include <xen/init.h>
-#include <asm/mach_ipi.h>
-#include <asm/mach-es7000/mach_apic.h>
 #include <asm/mach-es7000/mach_mpparse.h>
 
 static __init int probe_es7000(void)
@@ -25,5 +23,5 @@ static __init int probe_es7000(void)
 
 struct genapic apic_es7000 = {
 	APIC_INIT("es7000", probe_es7000),
-	.send_ipi_mask = send_IPI_mask_sequence
+	GENAPIC_PHYS
 };
diff --git a/xen/arch/x86/genapic/summit.c b/xen/arch/x86/genapic/summit.c
index acf191acfc..837a5ad85d 100644
--- a/xen/arch/x86/genapic/summit.c
+++ b/xen/arch/x86/genapic/summit.c
@@ -12,8 +12,6 @@
 #include <xen/string.h>
 #include <xen/smp.h>
 #include <xen/init.h>
-#include <asm/mach_ipi.h>
-#include <asm/mach-summit/mach_apic.h>
 #include <asm/mach-summit/mach_mpparse.h>
 
 static __init int probe_summit(void)
@@ -24,5 +22,5 @@ static __init int probe_summit(void)
 
 struct genapic apic_summit = {
 	APIC_INIT("summit", probe_summit),
-	.send_ipi_mask = send_IPI_mask_sequence
+	GENAPIC_PHYS
 };