x86: Replace FLUSH_LEVEL() parameter to flush_area() with rather

clearer FLUSH_ORDER(). Also remove bogus assertion.
Signed-off-by: Keir Fraser <keir@xensource.com>

1 files changed, 7 insertions, 9 deletions

diff --git a/xen/arch/x86/flushtlb.c b/xen/arch/x86/flushtlb.c
index 808b848de5..cb0fbb7580 100644
--- a/xen/arch/x86/flushtlb.c
+++ b/xen/arch/x86/flushtlb.c
@@ -98,17 +98,15 @@ void write_cr3(unsigned long cr3)
 void flush_area_local(const void *va, unsigned int flags)
 {
     const struct cpuinfo_x86 *c = &current_cpu_data;
-    unsigned int level = flags & FLUSH_LEVEL_MASK;
+    unsigned int order = (flags - 1) & FLUSH_ORDER_MASK;
     unsigned long irqfl;
 
-    ASSERT(level < CONFIG_PAGING_LEVELS);
-
     /* This non-reentrant function is sometimes called in interrupt context. */
     local_irq_save(irqfl);
 
     if ( flags & (FLUSH_TLB|FLUSH_TLB_GLOBAL) )
     {
-        if ( level == 1 )
+        if ( order == 0 )
         {
             /*
              * We don't INVLPG multi-page regions because the 2M/4M/1G
@@ -146,14 +144,14 @@ void flush_area_local(const void *va, unsigned int flags)
 
     if ( flags & FLUSH_CACHE )
     {
-        unsigned long i, sz;
+        unsigned long i, sz = 0;
 
-        sz = level ? (1UL << ((level - 1) * PAGETABLE_ORDER)) : ULONG_MAX;
+        if ( order < (BITS_PER_LONG - PAGE_SHIFT - 1) )
+            sz = 1UL << (order + PAGE_SHIFT);
 
-        if ( c->x86_clflush_size && c->x86_cache_size &&
-             (sz < (c->x86_cache_size >> (PAGE_SHIFT - 10))) )
+        if ( c->x86_clflush_size && c->x86_cache_size && sz &&
+             ((sz >> 10) < c->x86_cache_size) )
         {
-            sz <<= PAGE_SHIFT;
             va = (const void *)((unsigned long)va & ~(sz - 1));
             for ( i = 0; i < sz; i += c->x86_clflush_size )
                  asm volatile ( "clflush %0"