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| author | Keir Fraser <keir.fraser@citrix.com> | 2008-09-22 13:46:57 +0100 |
|---|---|---|
| committer | Keir Fraser <keir.fraser@citrix.com> | 2008-09-22 13:46:57 +0100 |
| commit | a0c61c0f77d2e0926bf728623e474fe9126648ae (patch) | |
| tree | 1ed061a7b59d162a5b33b11ea9dfc38e95fe28f3 /xen/arch/x86/boot/x86_64.S | |
| parent | 27e019d758f4aa3cdbae469fb9c2fada5a021cfa (diff) | |
| download | xen-a0c61c0f77d2e0926bf728623e474fe9126648ae.tar.gz xen-a0c61c0f77d2e0926bf728623e474fe9126648ae.tar.bz2 xen-a0c61c0f77d2e0926bf728623e474fe9126648ae.zip | |
x86: make GDT per-CPU
The major issue with supporting a significantly larger number of
physical CPUs appears to be the use of per-CPU GDT entries - at
present, x86-64 could support only up to 126 CPUs (with code changes
to also use the top-most GDT page, that would be 254). Instead of
trying to go with incremental steps here, by converting the GDT itself
to be per-CPU, limitations in that respect go away entirely.
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Diffstat (limited to 'xen/arch/x86/boot/x86_64.S')
| -rw-r--r-- | xen/arch/x86/boot/x86_64.S | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/xen/arch/x86/boot/x86_64.S b/xen/arch/x86/boot/x86_64.S index 07756e9024..7932f8aaa9 100644 --- a/xen/arch/x86/boot/x86_64.S +++ b/xen/arch/x86/boot/x86_64.S @@ -85,7 +85,7 @@ multiboot_ptr: .word 0 gdt_descr: .word LAST_RESERVED_GDT_BYTE - .quad gdt_table - FIRST_RESERVED_GDT_BYTE + .quad boot_cpu_gdt_table - FIRST_RESERVED_GDT_BYTE .word 0,0,0 idt_descr: @@ -96,7 +96,7 @@ ENTRY(stack_start) .quad cpu0_stack .align PAGE_SIZE, 0 -ENTRY(gdt_table) +ENTRY(boot_cpu_gdt_table) .quad 0x0000000000000000 /* unused */ .quad 0x00af9a000000ffff /* 0xe008 ring 0 code, 64-bit mode */ .quad 0x00cf92000000ffff /* 0xe010 ring 0 data */ @@ -105,11 +105,13 @@ ENTRY(gdt_table) .quad 0x00cff2000000ffff /* 0xe02b ring 3 data */ .quad 0x00affa000000ffff /* 0xe033 ring 3 code, 64-bit mode */ .quad 0x00cf9a000000ffff /* 0xe038 ring 0 code, compatibility */ + .fill (PER_CPU_GDT_ENTRY - __HYPERVISOR_CS32 / 8 - 1), 8, 0 + .quad 0x0000910000000000 /* per-CPU entry (limit == cpu) */ .align PAGE_SIZE, 0 /* NB. Even rings != 0 get access to the full 4Gb, as only the */ /* (compatibility) machine->physical mapping table lives there. */ -ENTRY(compat_gdt_table) +ENTRY(boot_cpu_compat_gdt_table) .quad 0x0000000000000000 /* unused */ .quad 0x00af9a000000ffff /* 0xe008 ring 0 code, 64-bit mode */ .quad 0x00cf92000000ffff /* 0xe010 ring 0 data */ @@ -118,4 +120,6 @@ ENTRY(compat_gdt_table) .quad 0x00cffa000000ffff /* 0xe02b ring 3 code, compatibility */ .quad 0x00cff2000000ffff /* 0xe033 ring 3 data */ .quad 0x00cf9a000000ffff /* 0xe038 ring 0 code, compatibility */ + .fill (PER_CPU_GDT_ENTRY - __HYPERVISOR_CS32 / 8 - 1), 8, 0 + .quad 0x0000910000000000 /* per-CPU entry (limit == cpu) */ .align PAGE_SIZE, 0 |