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authorKeir Fraser <keir.fraser@citrix.com>2009-11-25 14:05:28 +0000
committerKeir Fraser <keir.fraser@citrix.com>2009-11-25 14:05:28 +0000
commit08a0b4ab0d193b8fbb9270b7ab26f527535ba69c (patch)
treecdef74bb4aeb86dfa80bcac7637500b547780731 /tools/examples
parent83371c34bc5a2eed015a5d034cd82ec243659d85 (diff)
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Replace tsc_native config option with tsc_mode config option
(NOTE: pvrdtscp mode not finished yet, but all other modes have been tested so sooner seemed better than later to submit this fairly major patch so we can get more mileage on it before next release.) New tsc_mode config option supercedes tsc_native and offers a more intelligent default and an additional option for intelligent apps running on PV domains ("pvrdtscp"). For PV domains, default mode will determine if the initial host has a "safe"** TSC (meaning it is always synchronized across all physical CPUs). If so, all domains will execute all rdtsc instructions natively; if not, all domains will emulate all rdtsc instructions but providing the TSC hertz rate of the initial machine. After being restored or live-migrated, all PV domains will emulate all rdtsc instructions. Hence, this default mode guarantees correctness while providing native performance in most conditions. For PV domains, tsc_mode==1 will always emulate rdtsc and tsc_mode==2 will never emulate rdtsc. For tsc_mode==3, rdtsc will never be emulated, but information is provided through pvcpuid instructions and rdtscp instructions so that an app can obtain "safe" pvclock-like TSC information across save/restore and live migration. (Will be completed in a follow-on patch.) For HVM domains, the default mode and "always emulate" mode do the same as tsc_native==0; the other two modes do the same as tsc_native==1. (HVM domains since 3.4 have implemented a tsc_mode=default-like functionality, but also can preserve native TSC across save/restore and live-migration IFF the initial and target machines have a common TSC cycle rate.) ** All newer AMD machines, and Nehalem and future Intel machines have "Invariant TSC"; many newer Intel machines have "Constant TSC" and do not support deep-C sleep states; these and all single-processor machines are "safe". Signed-off-by: Dan Magenheimer <dan.magenheimer@oracle.com>
Diffstat (limited to 'tools/examples')
-rw-r--r--tools/examples/xmexample.hvm11
1 files changed, 8 insertions, 3 deletions
diff --git a/tools/examples/xmexample.hvm b/tools/examples/xmexample.hvm
index e5ae97f966..09edda6aac 100644
--- a/tools/examples/xmexample.hvm
+++ b/tools/examples/xmexample.hvm
@@ -178,11 +178,16 @@ stdvga=0
serial='pty'
#----------------------------------------------------------------------------
-# tsc_native : TSC mode (0=emulate TSC, 1=native TSC)
+# tsc_mode : TSC mode (0=default, 1=native TSC, 2=never emulate, 3=pvrdtscp)
# emulate TSC provides synced TSC for all vcpus, but lose perfomrance.
# native TSC leverages hardware's TSC(no perf loss), but vcpu's TSC may lose
-# sync due to hardware's unreliable/unsynced TSC between CPUs.
-tsc_native=1
+# sync due to hardware's unreliable/unsynced TSC between CPUs.
+# default intelligently uses native TSC on machines where it is safe, but
+# switches to emulated if necessary after save/restore/migration
+# pvrdtscp is for intelligent apps that use special Xen-only paravirtualized
+# cpuid instructions to obtain offset/scaling/migration info and maximize
+# performance within pools of machines that support the rdtscp instruction
+tsc_mode=0
#-----------------------------------------------------------------------------
# Qemu Monitor, default is disable