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| author | Jan Beulich <jbeulich@suse.com> | 2012-12-05 09:52:14 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2012-12-05 09:52:14 +0100 |
| commit | dda3fb206c1d0dbb350dc61bc97124c80f315083 (patch) | |
| tree | 54b6dbd987f21e4af2b7b6d80d27566f4f672db6 /extras | |
| parent | e662eca49cf7c6ab16f874331b6893649b5cfee7 (diff) | |
| download | xen-dda3fb206c1d0dbb350dc61bc97124c80f315083.tar.gz xen-dda3fb206c1d0dbb350dc61bc97124c80f315083.tar.bz2 xen-dda3fb206c1d0dbb350dc61bc97124c80f315083.zip | |
IOMMU/ATS: fix maximum queue depth calculation
The capabilities register field is a 5-bit value, and the 5 bits all
being zero actually means 32 entries.
Under the assumption that amd_iommu_flush_iotlb() really just tried
to correct for the miscalculation above when adding 32 to the value,
that adjustment is also being removed.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by Xiantao Zhang <xiantao.zhang@intel.com>
Acked-by: Wei Huang <wei.huang2@amd.com>
Diffstat (limited to 'extras')
0 files changed, 0 insertions, 0 deletions