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| author | Keir Fraser <keir.fraser@citrix.com> | 2008-05-05 10:16:06 +0100 |
|---|---|---|
| committer | Keir Fraser <keir.fraser@citrix.com> | 2008-05-05 10:16:06 +0100 |
| commit | e8ffde4799525eb8b90c650b79626a141e5a94f3 (patch) | |
| tree | c730dce9ffe50e3a6d0b588d90a3e9ce379fc5c1 | |
| parent | cf177e383a094b6c769c6726c0327771392e1324 (diff) | |
| download | xen-e8ffde4799525eb8b90c650b79626a141e5a94f3.tar.gz xen-e8ffde4799525eb8b90c650b79626a141e5a94f3.tar.bz2 xen-e8ffde4799525eb8b90c650b79626a141e5a94f3.zip | |
Enable Px/Cx related CPUID/MSR bits for dom0 to get correct Px/Cx info.
Signed-off-by: Wei Gang <gang.wei@intel.com>
| -rw-r--r-- | xen/arch/x86/traps.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 75997500bc..ebdf25db4f 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -713,11 +713,13 @@ static int emulate_forced_invalid_op(struct cpu_user_regs *regs) __clear_bit(X86_FEATURE_PBE, &d); __clear_bit(X86_FEATURE_DTES64 % 32, &c); - __clear_bit(X86_FEATURE_MWAIT % 32, &c); + if ( !IS_PRIV(current->domain) ) + __clear_bit(X86_FEATURE_MWAIT % 32, &c); __clear_bit(X86_FEATURE_DSCPL % 32, &c); __clear_bit(X86_FEATURE_VMXE % 32, &c); __clear_bit(X86_FEATURE_SMXE % 32, &c); - __clear_bit(X86_FEATURE_EST % 32, &c); + if ( !IS_PRIV(current->domain) ) + __clear_bit(X86_FEATURE_EST % 32, &c); __clear_bit(X86_FEATURE_TM2 % 32, &c); if ( is_pv_32bit_vcpu(current) ) __clear_bit(X86_FEATURE_CX16 % 32, &c); @@ -2146,8 +2148,9 @@ static int emulate_privileged_op(struct cpu_user_regs *regs) case MSR_IA32_MISC_ENABLE: if ( rdmsr_safe(regs->ecx, regs->eax, regs->edx) ) goto fail; - regs->eax &= ~(MSR_IA32_MISC_ENABLE_PERF_AVAIL | - MSR_IA32_MISC_ENABLE_MONITOR_ENABLE); + regs->eax &= ~MSR_IA32_MISC_ENABLE_PERF_AVAIL; + if ( !IS_PRIV(current->domain) ) + regs->eax &= ~MSR_IA32_MISC_ENABLE_MONITOR_ENABLE; regs->eax |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL | MSR_IA32_MISC_ENABLE_XTPR_DISABLE; |