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| author | Jan Beulich <jbeulich@suse.com> | 2012-02-24 09:03:43 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2012-02-24 09:03:43 +0100 |
| commit | b272353fe98db5bdc73fff3c60a0574835df4c87 (patch) | |
| tree | 55a09f044c0779ae21bc1a8da2006eeec86292e6 | |
| parent | 8295fa0d827768695eab81ce6c950a575cfec47b (diff) | |
| download | xen-b272353fe98db5bdc73fff3c60a0574835df4c87.tar.gz xen-b272353fe98db5bdc73fff3c60a0574835df4c87.tar.bz2 xen-b272353fe98db5bdc73fff3c60a0574835df4c87.zip | |
x86/vMCE: don't advertise features we don't support
... or even know of. Apart from CMCI, which was masked off already,
this now also suppresses the advertising of extended state registers
(reading of which would likely be meaningless in a guest and represent
an information leak).
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Keir Fraser <keir@xen.org>
| -rw-r--r-- | xen/arch/x86/cpu/mcheck/vmce.c | 2 | ||||
| -rw-r--r-- | xen/arch/x86/cpu/mcheck/x86_mca.h | 11 |
2 files changed, 7 insertions, 6 deletions
diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index 2eadfb9f8d..ac9cb8422e 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -457,7 +457,7 @@ int vmce_init(struct cpuinfo_x86 *c) rdmsrl(MSR_IA32_MCG_CAP, value); /* For Guest vMCE usage */ - g_mcg_cap = value & ~MCG_CMCI_P; + g_mcg_cap = value & (MCG_CAP_COUNT | MCG_CTL_P | MCG_TES_P | MCG_SER_P); if (value & MCG_CTL_P) rdmsrl(MSR_IA32_MCG_CTL, h_mcg_ctl); diff --git a/xen/arch/x86/cpu/mcheck/x86_mca.h b/xen/arch/x86/cpu/mcheck/x86_mca.h index 2a91f3ae26..885d7ba21a 100644 --- a/xen/arch/x86/cpu/mcheck/x86_mca.h +++ b/xen/arch/x86/cpu/mcheck/x86_mca.h @@ -30,12 +30,13 @@ /* Bitfield of the MSR_IA32_MCG_CAP register */ -#define MCG_SER_P (1UL<<24) #define MCG_CAP_COUNT 0x00000000000000ffULL -#define MCG_CTL_P 0x0000000000000100ULL -#define MCG_EXT_P (1UL<<9) -#define MCG_EXT_CNT (16) -#define MCG_CMCI_P (1UL<<10) +#define MCG_CTL_P (1ULL<<8) +#define MCG_EXT_P (1ULL<<9) +#define MCG_CMCI_P (1ULL<<10) +#define MCG_TES_P (1ULL<<11) +#define MCG_EXT_CNT 16 +#define MCG_SER_P (1ULL<<24) /* Other bits are reserved */ /* Bitfield of the MSR_IA32_MCG_STATUS register */ |