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authorTim Deegan <Tim.Deegan@citrix.com>2011-03-07 11:21:11 +0000
committerTim Deegan <Tim.Deegan@citrix.com>2011-03-07 11:21:11 +0000
commit794d4b9e85047aacfe23b852d3a03a8eff920aec (patch)
treed69055821426f9154568cbae37587823f2d23997
parent26315747810e1a520daeb5fc0042ab083dead693 (diff)
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x86: add explicit size suffixes to some assembly instructions.
This is needed to compile xen with clang. Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com> Acked-by: Keir Fraser <keir@xen.org>
-rw-r--r--xen/arch/x86/acpi/suspend.c4
-rw-r--r--xen/arch/x86/x86_emulate/x86_emulate.c26
2 files changed, 15 insertions, 15 deletions
diff --git a/xen/arch/x86/acpi/suspend.c b/xen/arch/x86/acpi/suspend.c
index 6f2ff5b82b..0291ea8f34 100644
--- a/xen/arch/x86/acpi/suspend.c
+++ b/xen/arch/x86/acpi/suspend.c
@@ -28,7 +28,7 @@ void save_rest_processor_state(void)
#if defined(CONFIG_X86_64)
asm volatile (
- "mov %%ds,(%0); mov %%es,2(%0); mov %%fs,4(%0); mov %%gs,6(%0)"
+ "movw %%ds,(%0); movw %%es,2(%0); movw %%fs,4(%0); movw %%gs,6(%0)"
: : "r" (saved_segs) : "memory" );
rdmsrl(MSR_FS_BASE, saved_fs_base);
rdmsrl(MSR_GS_BASE, saved_gs_base);
@@ -75,7 +75,7 @@ void restore_rest_processor_state(void)
if ( !is_idle_vcpu(curr) )
{
asm volatile (
- "mov (%0),%%ds; mov 2(%0),%%es; mov 4(%0),%%fs"
+ "movw (%0),%%ds; movw 2(%0),%%es; movw 4(%0),%%fs"
: : "r" (saved_segs) : "memory" );
do_set_segment_base(SEGBASE_GS_USER_SEL, saved_segs[3]);
}
diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index 186cef2b9b..babde81ff3 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -2678,7 +2678,7 @@ x86_emulate(
emulate_fpu_insn_memsrc("fiaddl", src.val);
break;
case 1: /* fimul m64i */
- emulate_fpu_insn_memsrc("fimul", src.val);
+ emulate_fpu_insn_memsrc("fimuls", src.val);
break;
case 2: /* ficom m64i */
emulate_fpu_insn_memsrc("ficoml", src.val);
@@ -2897,28 +2897,28 @@ x86_emulate(
switch ( modrm_reg & 7 )
{
case 0: /* fiadd m16i */
- emulate_fpu_insn_memsrc("fiadd", src.val);
+ emulate_fpu_insn_memsrc("fiadds", src.val);
break;
case 1: /* fimul m16i */
- emulate_fpu_insn_memsrc("fimul", src.val);
+ emulate_fpu_insn_memsrc("fimuls", src.val);
break;
case 2: /* ficom m16i */
- emulate_fpu_insn_memsrc("ficom", src.val);
+ emulate_fpu_insn_memsrc("ficoms", src.val);
break;
case 3: /* ficomp m16i */
- emulate_fpu_insn_memsrc("ficomp", src.val);
+ emulate_fpu_insn_memsrc("ficomps", src.val);
break;
case 4: /* fisub m16i */
- emulate_fpu_insn_memsrc("fisub", src.val);
+ emulate_fpu_insn_memsrc("fisubs", src.val);
break;
case 5: /* fisubr m16i */
- emulate_fpu_insn_memsrc("fisubr", src.val);
+ emulate_fpu_insn_memsrc("fisubrs", src.val);
break;
case 6: /* fidiv m16i */
- emulate_fpu_insn_memsrc("fidiv", src.val);
+ emulate_fpu_insn_memsrc("fidivs", src.val);
break;
case 7: /* fidivr m16i */
- emulate_fpu_insn_memsrc("fidivr", src.val);
+ emulate_fpu_insn_memsrc("fidivrs", src.val);
break;
default:
goto cannot_emulate;
@@ -2950,25 +2950,25 @@ x86_emulate(
if ( (rc = ops->read(src.mem.seg, src.mem.off, &src.val,
src.bytes, ctxt)) != 0 )
goto done;
- emulate_fpu_insn_memsrc("fild", src.val);
+ emulate_fpu_insn_memsrc("filds", src.val);
break;
case 1: /* fisttp m16i */
ea.bytes = 2;
dst = ea;
dst.type = OP_MEM;
- emulate_fpu_insn_memdst("fisttp", dst.val);
+ emulate_fpu_insn_memdst("fisttps", dst.val);
break;
case 2: /* fist m16i */
ea.bytes = 2;
dst = ea;
dst.type = OP_MEM;
- emulate_fpu_insn_memdst("fist", dst.val);
+ emulate_fpu_insn_memdst("fists", dst.val);
break;
case 3: /* fistp m16i */
ea.bytes = 2;
dst = ea;
dst.type = OP_MEM;
- emulate_fpu_insn_memdst("fistp", dst.val);
+ emulate_fpu_insn_memdst("fistps", dst.val);
break;
case 4: /* fbld m80dec */
ea.bytes = 10;