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| author | Keir Fraser <keir@xensource.com> | 2007-10-24 10:20:03 +0100 |
|---|---|---|
| committer | Keir Fraser <keir@xensource.com> | 2007-10-24 10:20:03 +0100 |
| commit | 6cf492cfe939329af84780ec3b9a7aff954077ac (patch) | |
| tree | 1ef55baeff6a915c8cc7c715264d4706eb04487b | |
| parent | 3aea90a30cd06f7c8fb33114944cac45f68b6756 (diff) | |
| download | xen-6cf492cfe939329af84780ec3b9a7aff954077ac.tar.gz xen-6cf492cfe939329af84780ec3b9a7aff954077ac.tar.bz2 xen-6cf492cfe939329af84780ec3b9a7aff954077ac.zip | |
x86, cpufreq: Allow dom0 kernel to govern cpufreq via the Intel
Enahanced SpeedStep MSR.
From: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Keir Fraser <keir@xensource.com>
| -rw-r--r-- | xen/arch/x86/traps.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 8ccbeee2c6..0aa8c8ba54 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -1773,6 +1773,12 @@ static int emulate_privileged_op(struct cpu_user_regs *regs) wrmsr_safe(regs->ecx, eax, edx) ) goto fail; break; + case MSR_IA32_PERF_CTL: + if ( (cpufreq_controller != FREQCTL_dom0_kernel) || + (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) || + wrmsr_safe(regs->ecx, eax, edx) ) + goto fail; + break; default: if ( wrmsr_hypervisor_regs(regs->ecx, eax, edx) ) break; |