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| author | Liu, Jinsong <jinsong.liu@intel.com> | 2012-02-28 09:06:27 +0100 |
|---|---|---|
| committer | Liu, Jinsong <jinsong.liu@intel.com> | 2012-02-28 09:06:27 +0100 |
| commit | 6af7deded7aae2a90c7eec5e7b1ce053362e73f0 (patch) | |
| tree | 5851e94ba533e0f1a7c1fcd521581a15db5e8aba | |
| parent | 2e20f9102daf651f096eedb112661396d16c2e09 (diff) | |
| download | xen-6af7deded7aae2a90c7eec5e7b1ce053362e73f0.tar.gz xen-6af7deded7aae2a90c7eec5e7b1ce053362e73f0.tar.bz2 xen-6af7deded7aae2a90c7eec5e7b1ce053362e73f0.zip | |
X86: expose HLE/RTM features to dom0
Intel recently release 2 new features, HLE and TRM.
Refer to http://software.intel.com/file/41417.
This patch expose them to dom0.
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
Committed-by: Jan Beulich <jbeulich@suse.com>
| -rw-r--r-- | xen/arch/x86/traps.c | 2 | ||||
| -rw-r--r-- | xen/include/asm-x86/cpufeature.h | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 286f1a2954..56b4115982 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -857,9 +857,11 @@ static void pv_cpuid(struct cpu_user_regs *regs) case 0x00000007: if ( regs->ecx == 0 ) b &= (cpufeat_mask(X86_FEATURE_BMI1) | + cpufeat_mask(X86_FEATURE_HLE) | cpufeat_mask(X86_FEATURE_AVX2) | cpufeat_mask(X86_FEATURE_BMI2) | cpufeat_mask(X86_FEATURE_ERMS) | + cpufeat_mask(X86_FEATURE_RTM) | cpufeat_mask(X86_FEATURE_FSGSBASE)); else b = 0; diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h index e24d5244b4..e31f32713c 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -149,11 +149,13 @@ /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 7 */ #define X86_FEATURE_FSGSBASE (7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */ #define X86_FEATURE_BMI1 (7*32+ 3) /* 1st bit manipulation extensions */ +#define X86_FEATURE_HLE (7*32+ 4) /* Hardware Lock Elision */ #define X86_FEATURE_AVX2 (7*32+ 5) /* AVX2 instructions */ #define X86_FEATURE_SMEP (7*32+ 7) /* Supervisor Mode Execution Protection */ #define X86_FEATURE_BMI2 (7*32+ 8) /* 2nd bit manipulation extensions */ #define X86_FEATURE_ERMS (7*32+ 9) /* Enhanced REP MOVSB/STOSB */ #define X86_FEATURE_INVPCID (7*32+10) /* Invalidate Process Context ID */ +#define X86_FEATURE_RTM (7*32+11) /* Restricted Transactional Memory */ #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) #define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability) |