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| author | Liu, Jinsong <jinsong.liu@intel.com> | 2011-12-01 12:21:24 +0100 |
|---|---|---|
| committer | Liu, Jinsong <jinsong.liu@intel.com> | 2011-12-01 12:21:24 +0100 |
| commit | 500161db50e3430026b5374462c1bdac00257abe (patch) | |
| tree | 1fd9a03c26cc601065427e2808602beaace4e858 | |
| parent | eec25c2300cd3da0fef95159e7ed7932fc31dca9 (diff) | |
| download | xen-500161db50e3430026b5374462c1bdac00257abe.tar.gz xen-500161db50e3430026b5374462c1bdac00257abe.tar.bz2 xen-500161db50e3430026b5374462c1bdac00257abe.zip | |
X86: expose Intel new features to dom0
This patch expose Intel new features to dom0, including
FMA/AVX2/BMI1/BMI2/LZCNT/MOVBE.
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
Committed-by: Jan Beulich <jbeulich@suse.com>
| -rw-r--r-- | xen/arch/x86/traps.c | 7 | ||||
| -rw-r--r-- | xen/include/asm-x86/cpufeature.h | 5 |
2 files changed, 10 insertions, 2 deletions
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index d6e9c0ccb3..03dc7c3501 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -854,8 +854,11 @@ static void pv_cpuid(struct cpu_user_regs *regs) case 0x00000007: if ( regs->ecx == 0 ) - b &= (cpufeat_mask(X86_FEATURE_FSGSBASE) | - cpufeat_mask(X86_FEATURE_ERMS)); + b &= (cpufeat_mask(X86_FEATURE_BMI1) | + cpufeat_mask(X86_FEATURE_AVX2) | + cpufeat_mask(X86_FEATURE_BMI2) | + cpufeat_mask(X86_FEATURE_ERMS) | + cpufeat_mask(X86_FEATURE_FSGSBASE)); else b = 0; a = c = d = 0; diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h index a1b52edd2d..776333a75f 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -93,6 +93,7 @@ #define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */ #define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental Streaming SIMD Extensions-3 */ #define X86_FEATURE_CID (4*32+10) /* Context ID */ +#define X86_FEATURE_FMA (4*32+12) /* Fused Multiply Add */ #define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */ #define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */ #define X86_FEATURE_PDCM (4*32+15) /* Perf/Debug Capability MSR */ @@ -100,6 +101,7 @@ #define X86_FEATURE_SSE4_1 (4*32+19) /* Streaming SIMD Extensions 4.1 */ #define X86_FEATURE_SSE4_2 (4*32+20) /* Streaming SIMD Extensions 4.2 */ #define X86_FEATURE_X2APIC (4*32+21) /* Extended xAPIC */ +#define X86_FEATURE_MOVBE (4*32+22) /* movbe instruction */ #define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */ #define X86_FEATURE_TSC_DEADLINE (4*32+24) /* "tdt" TSC Deadline Timer */ #define X86_FEATURE_AES (4*32+25) /* AES instructions */ @@ -145,7 +147,10 @@ /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 7 */ #define X86_FEATURE_FSGSBASE (7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */ +#define X86_FEATURE_BMI1 (7*32+ 3) /* 1st bit manipulation extensions */ +#define X86_FEATURE_AVX2 (7*32+ 5) /* AVX2 instructions */ #define X86_FEATURE_SMEP (7*32+ 7) /* Supervisor Mode Execution Protection */ +#define X86_FEATURE_BMI2 (7*32+ 8) /* 2nd bit manipulation extensions */ #define X86_FEATURE_ERMS (7*32+ 9) /* Enhanced REP MOVSB/STOSB */ #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) |