x86: adjust other interrupt related section placement

... and remove some variables the value of which is never used
altogether.

Signed-off-by: Jan Beulich <jbeulich@novell.com>

8 files changed, 9 insertions, 33 deletions

diff --git a/xen/arch/ia64/xen/irq.c b/xen/arch/ia64/xen/irq.c
index 405f3feea9..c18a0d0ca0 100644
--- a/xen/arch/ia64/xen/irq.c
+++ b/xen/arch/ia64/xen/irq.c
@@ -128,8 +128,6 @@ hw_irq_controller no_irq_type = {
 	end_none
 };
 
-atomic_t irq_err_count;
-
 /*
  * Generic enable/disable code: this just calls
  * down into the PIC-specific version for the actual
diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c
index f48c442e39..b05a9b7eb9 100644
--- a/xen/arch/x86/apic.c
+++ b/xen/arch/x86/apic.c
@@ -160,7 +160,7 @@ void __init apic_intr_init(void)
 }
 
 /* Using APIC to generate smp_local_timer_interrupt? */
-int using_apic_timer = 0;
+static bool_t __read_mostly using_apic_timer;
 
 static int enabled_via_apicbase;
 
@@ -1083,9 +1083,7 @@ __next:
  *****************************************************************************/
 
 /* used for system time scaling */
-static unsigned long bus_freq;    /* KAF: pointer-size avoids compile warns. */
-static u32           bus_cycle;   /* length of one bus cycle in pico-seconds */
-static u32           bus_scale;   /* scaling factor convert ns to bus cycles */
+static u32 __read_mostly bus_scale; /* scaling factor convert ns to bus cycles */
 
 /*
  * The timer chip is already set up at HZ interrupts per second here,
@@ -1197,6 +1195,8 @@ static int __init calibrate_APIC_clock(void)
     long tt1, tt2;
     long result;
     int i;
+    unsigned long bus_freq; /* KAF: pointer-size avoids compile warns. */
+    u32 bus_cycle;          /* length of one bus cycle in pico-seconds */
     const int LOOPS = HZ/10;
 
     apic_printk(APIC_VERBOSE, "calibrating APIC timer ...\n");
@@ -1411,7 +1411,6 @@ fastcall void smp_error_interrupt(struct cpu_user_regs *regs)
     apic_write(APIC_ESR, 0);
     v1 = apic_read(APIC_ESR);
     ack_APIC_irq();
-    atomic_inc(&irq_err_count);
 
     /* Here is what the APIC error bits mean:
        0: Send CS error
diff --git a/xen/arch/x86/i8259.c b/xen/arch/x86/i8259.c
index 7e4722c627..93ba9ffc3a 100644
--- a/xen/arch/x86/i8259.c
+++ b/xen/arch/x86/i8259.c
@@ -284,7 +284,6 @@ static void mask_and_ack_8259A_irq(unsigned int irq)
             printk("spurious 8259A interrupt: IRQ%d.\n", irq);
             spurious_irq_mask |= irqmask;
         }
-        atomic_inc(&irq_err_count);
         /*
          * Theoretically we do not have to handle this IRQ,
          * but in Linux this does not cause problems and is
diff --git a/xen/arch/x86/io_apic.c b/xen/arch/x86/io_apic.c
index 401f2ecd3f..dfcf13258d 100644
--- a/xen/arch/x86/io_apic.c
+++ b/xen/arch/x86/io_apic.c
@@ -38,8 +38,6 @@
 #include <io_ports.h>
 #include <public/physdev.h>
 
-atomic_t irq_mis_count;
-
 /* Where if anywhere is the i8259 connect in external int mode */
 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
 
@@ -61,8 +59,6 @@ int sis_apic_bug = -1;
 int __read_mostly nr_ioapic_registers[MAX_IO_APICS];
 int __read_mostly nr_ioapics;
 
-int disable_timer_pin_1 __initdata;
-
 /*
  * Rough estimation of how many shared IRQs there are, can
  * be changed anytime.
@@ -1641,7 +1637,6 @@ static void mask_and_ack_level_ioapic_irq (unsigned int irq)
         move_masked_irq(irq);
 
     if ( !(v & (1 << (i & 0x1f))) ) {
-        atomic_inc(&irq_mis_count);
         spin_lock(&ioapic_lock);
         __edge_IO_APIC_irq(irq);
         __level_IO_APIC_irq(irq);
@@ -1707,7 +1702,6 @@ static void end_level_ioapic_irq (unsigned int irq)
         move_native_irq(irq);
 
     if (!(v & (1 << (i & 0x1f)))) {
-        atomic_inc(&irq_mis_count);
         spin_lock(&ioapic_lock);
         __mask_IO_APIC_irq(irq);
         __edge_IO_APIC_irq(irq);
@@ -1845,7 +1839,7 @@ static hw_irq_controller lapic_irq_type = {
  * cycles as some i82489DX-based boards have glue logic that keeps the
  * 8259A interrupt line asserted until INTA.  --macro
  */
-static inline void unlock_ExtINT_logic(void)
+static void __init unlock_ExtINT_logic(void)
 {
     int apic, pin, i;
     struct IO_APIC_route_entry entry0, entry1;
@@ -1902,15 +1896,13 @@ static inline void unlock_ExtINT_logic(void)
     spin_unlock_irqrestore(&ioapic_lock, flags);
 }
 
-int timer_uses_ioapic_pin_0;
-
 /*
  * This code may look a bit paranoid, but it's supposed to cooperate with
  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
  * fanatically on his truly buggy board.
  */
-static inline void check_timer(void)
+static void __init check_timer(void)
 {
     int apic1, pin1, apic2, pin2;
     int vector, ret;
@@ -1949,9 +1941,6 @@ static inline void check_timer(void)
     pin2  = ioapic_i8259.pin;
     apic2 = ioapic_i8259.apic;
 
-    if (pin1 == 0)
-        timer_uses_ioapic_pin_0 = 1;
-
     printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
            vector, apic1, pin1, apic2, pin2);
 
@@ -1962,8 +1951,6 @@ static inline void check_timer(void)
         unmask_IO_APIC_irq(0);
         if (timer_irq_works()) {
             local_irq_restore(flags);
-            if (disable_timer_pin_1 > 0)
-                clear_IO_APIC_pin(apic1, pin1);
             return;
         }
         clear_IO_APIC_pin(apic1, pin1);
@@ -2131,7 +2118,7 @@ void ioapic_resume(void)
 int __init io_apic_get_unique_id (int ioapic, int apic_id)
 {
     union IO_APIC_reg_00 reg_00;
-    static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
+    static physid_mask_t __initdata apic_id_map = PHYSID_MASK_NONE;
     physid_mask_t tmp;
     unsigned long flags;
     int i = 0;
diff --git a/xen/arch/x86/irq.c b/xen/arch/x86/irq.c
index 08610b7bdf..38c0108a72 100644
--- a/xen/arch/x86/irq.c
+++ b/xen/arch/x86/irq.c
@@ -74,7 +74,7 @@ void unlock_vector_lock(void)
     spin_unlock(&vector_lock);
 }
 
-static int __bind_irq_vector(int irq, int vector, cpumask_t cpu_mask)
+static int __init __bind_irq_vector(int irq, int vector, cpumask_t cpu_mask)
 {
     cpumask_t online_mask;
     int cpu;
@@ -100,7 +100,7 @@ static int __bind_irq_vector(int irq, int vector, cpumask_t cpu_mask)
     return 0;
 }
 
-int bind_irq_vector(int irq, int vector, cpumask_t cpu_mask)
+int __init bind_irq_vector(int irq, int vector, cpumask_t cpu_mask)
 {
     unsigned long flags;
     int ret;
@@ -328,8 +328,6 @@ hw_irq_controller no_irq_type = {
     end_none
 };
 
-atomic_t irq_err_count;
-
 int __assign_irq_vector(int irq, struct irq_cfg *cfg, const cpumask_t *mask)
 {
     /*
diff --git a/xen/include/asm-x86/io_apic.h b/xen/include/asm-x86/io_apic.h
index fcbb557325..07991aac74 100644
--- a/xen/include/asm-x86/io_apic.h
+++ b/xen/include/asm-x86/io_apic.h
@@ -190,7 +190,6 @@ extern int io_apic_get_unique_id (int ioapic, int apic_id);
 extern int io_apic_get_version (int ioapic);
 extern int io_apic_get_redir_entries (int ioapic);
 extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low);
-extern int timer_uses_ioapic_pin_0;
 #endif /*CONFIG_ACPI_BOOT*/
 
 extern void init_ioapic_mappings(void);
diff --git a/xen/include/asm-x86/irq.h b/xen/include/asm-x86/irq.h
index 601828973d..addb958895 100644
--- a/xen/include/asm-x86/irq.h
+++ b/xen/include/asm-x86/irq.h
@@ -102,9 +102,6 @@ void setup_ioapic_dest(void);
 
 extern unsigned long io_apic_irqs;
 
-extern atomic_t irq_err_count;
-extern atomic_t irq_mis_count;
-
 DECLARE_PER_CPU(unsigned int, irq_count);
 
 int pirq_shared(struct domain *d , int irq);
diff --git a/xen/include/asm-x86/mpspec.h b/xen/include/asm-x86/mpspec.h
index 4ad75cc2db..20abadfec4 100644
--- a/xen/include/asm-x86/mpspec.h
+++ b/xen/include/asm-x86/mpspec.h
@@ -21,7 +21,6 @@ extern struct mpc_config_intsrc mp_irqs [MAX_IRQ_SOURCES];
 extern int mpc_default_type;
 extern unsigned long mp_lapic_addr;
 extern int pic_mode;
-extern int using_apic_timer;
 
 #ifdef CONFIG_ACPI
 extern int mp_register_lapic (u32 id, u8 enabled);