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| author | Keir Fraser <keir.fraser@citrix.com> | 2010-06-21 10:03:11 +0100 |
|---|---|---|
| committer | Keir Fraser <keir.fraser@citrix.com> | 2010-06-21 10:03:11 +0100 |
| commit | 02803d18d72afad09d1e663847c0312bb5c10b28 (patch) | |
| tree | e45f2dba0ae1be3558f5f37f275acb24fc10264c | |
| parent | 91fdb82086dd62ba6952234a99f10fc23b873465 (diff) | |
| download | xen-02803d18d72afad09d1e663847c0312bb5c10b28.tar.gz xen-02803d18d72afad09d1e663847c0312bb5c10b28.tar.bz2 xen-02803d18d72afad09d1e663847c0312bb5c10b28.zip | |
vmx: Fix bug in VMX VPMU fixed function PMC offset
This is a minor fix to the calculation of bit-width of fixed function
perfmon counters in Intel processors. Bits 5-12 of edx register
should be calculated as (edx & 0x1fe0) >>5 instead of using 0x1f70.
From: "John, Jaiber J" <jaiber.j.john@intel.com>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
xen-unstable changeset: 21643:31708477f0a9
xen-unstable date: Mon Jun 21 09:59:10 2010 +0100
| -rw-r--r-- | xen/arch/x86/hvm/vmx/vpmu_core2.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c b/xen/arch/x86/hvm/vmx/vpmu_core2.c index 31ca46e7b5..dd72580091 100644 --- a/xen/arch/x86/hvm/vmx/vpmu_core2.c +++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c @@ -82,7 +82,7 @@ static int core2_get_bitwidth_fix_count(void) { u32 eax, ebx, ecx, edx; cpuid(0xa, &eax, &ebx, &ecx, &edx); - return ((edx & 0x1f70) >> 5); + return ((edx & 0x1fe0) >> 5); } static int is_core2_vpmu_msr(u32 msr_index, int *type, int *index) |