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| author | George Dunlap <george.dunlap@eu.citrix.com> | 2012-05-01 14:18:46 +0100 |
|---|---|---|
| committer | George Dunlap <george.dunlap@eu.citrix.com> | 2012-05-01 14:18:46 +0100 |
| commit | 506243e7644fb32bf7bfd7238d3c64be0ad14b91 (patch) | |
| tree | d04c282f2fc4928088ecbe10a1377ef910a4140a | |
| parent | b8d623e62afdf7d9ecfe98659dc9d004f983c6f8 (diff) | |
| download | xen-506243e7644fb32bf7bfd7238d3c64be0ad14b91.tar.gz xen-506243e7644fb32bf7bfd7238d3c64be0ad14b91.tar.bz2 xen-506243e7644fb32bf7bfd7238d3c64be0ad14b91.zip | |
svm: Fake out the Bus Unit Config MSR on revF AMD CPUs
Win2k8 x64 reads this MSR on revF chips, where it wasn't publically
available; it uses a magic constant in %rdi as a password, which we
don't have in rdmsr_safe(). Since we'll ignore the later writes, just
use a plausible value here (the reset value from rev10h chips) if the
real CPU didn't provide one.
Signed-off-by: George Dunlap <george.dunlap@eu.citrix.com>
Committed-by: Keir Fraser <keir@xen.org>
xen-unstable changeset: 24990:322300fd2ebd
xen-unstable date: Thu Mar 08 09:17:21 2012 +0000
svm: amend c/s 24990:322300fd2ebd (fake BU_CFG MSR on AMD revF)
Let's restrict such a hack to the known affected family.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Keir Fraser <keir@xen.org>
Acked-by: George Dunlap <george.dunlap@eu.citrix.com>
xen-unstable changeset: 25058:f47d91cb0faa
xen-unstable date: Thu Mar 15 15:09:18 2012 +0100
| -rw-r--r-- | xen/arch/x86/hvm/svm/svm.c | 12 | ||||
| -rw-r--r-- | xen/include/asm-x86/msr-index.h | 3 |
2 files changed, 15 insertions, 0 deletions
diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index f175216a28..134b8ebaaa 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -1070,6 +1070,18 @@ static int svm_msr_read_intercept(struct cpu_user_regs *regs) break; } + if ( boot_cpu_data.x86 == 0xf && ecx == MSR_F10_BU_CFG ) + { + /* Win2k8 x64 reads this MSR on revF chips, where it + * wasn't publically available; it uses a magic constant + * in %rdi as a password, which we don't have in + * rdmsr_safe(). Since we'll ignore the later writes, + * just use a plausible value here (the reset value from + * rev10h chips) if the real CPU didn't provide one. */ + msr_content = 0x0000000010200020ull; + break; + } + goto gpf; } diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index 3d54e2ca24..5f4d00693e 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -242,6 +242,9 @@ #define MSR_F10_MC4_MISC2 0xc0000409 #define MSR_F10_MC4_MISC3 0xc000040A +/* AMD Family10h MMU control MSRs */ +#define MSR_F10_BU_CFG 0xc0011023 + /* Other AMD Fam10h MSRs */ #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 #define FAM10H_MMIO_CONF_ENABLE (1<<0) |