From 506243e7644fb32bf7bfd7238d3c64be0ad14b91 Mon Sep 17 00:00:00 2001 From: George Dunlap Date: Tue, 1 May 2012 14:18:46 +0100 Subject: svm: Fake out the Bus Unit Config MSR on revF AMD CPUs Win2k8 x64 reads this MSR on revF chips, where it wasn't publically available; it uses a magic constant in %rdi as a password, which we don't have in rdmsr_safe(). Since we'll ignore the later writes, just use a plausible value here (the reset value from rev10h chips) if the real CPU didn't provide one. Signed-off-by: George Dunlap Committed-by: Keir Fraser xen-unstable changeset: 24990:322300fd2ebd xen-unstable date: Thu Mar 08 09:17:21 2012 +0000 svm: amend c/s 24990:322300fd2ebd (fake BU_CFG MSR on AMD revF) Let's restrict such a hack to the known affected family. Signed-off-by: Jan Beulich Acked-by: Keir Fraser Acked-by: George Dunlap xen-unstable changeset: 25058:f47d91cb0faa xen-unstable date: Thu Mar 15 15:09:18 2012 +0100 --- xen/arch/x86/hvm/svm/svm.c | 12 ++++++++++++ xen/include/asm-x86/msr-index.h | 3 +++ 2 files changed, 15 insertions(+) diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index f175216a28..134b8ebaaa 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -1070,6 +1070,18 @@ static int svm_msr_read_intercept(struct cpu_user_regs *regs) break; } + if ( boot_cpu_data.x86 == 0xf && ecx == MSR_F10_BU_CFG ) + { + /* Win2k8 x64 reads this MSR on revF chips, where it + * wasn't publically available; it uses a magic constant + * in %rdi as a password, which we don't have in + * rdmsr_safe(). Since we'll ignore the later writes, + * just use a plausible value here (the reset value from + * rev10h chips) if the real CPU didn't provide one. */ + msr_content = 0x0000000010200020ull; + break; + } + goto gpf; } diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index 3d54e2ca24..5f4d00693e 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -242,6 +242,9 @@ #define MSR_F10_MC4_MISC2 0xc0000409 #define MSR_F10_MC4_MISC3 0xc000040A +/* AMD Family10h MMU control MSRs */ +#define MSR_F10_BU_CFG 0xc0011023 + /* Other AMD Fam10h MSRs */ #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 #define FAM10H_MMIO_CONF_ENABLE (1<<0) -- cgit v1.2.3