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-rw-r--r--tboot/include/txt/acmod.h195
-rw-r--r--tboot/include/txt/config_regs.h240
-rw-r--r--tboot/include/txt/errorcode.h105
-rw-r--r--tboot/include/txt/heap.h377
-rw-r--r--tboot/include/txt/mtrrs.h149
-rw-r--r--tboot/include/txt/smx.h171
-rw-r--r--tboot/include/txt/txt.h76
-rw-r--r--tboot/include/txt/verify.h57
-rw-r--r--tboot/include/txt/vmcs.h346
9 files changed, 1716 insertions, 0 deletions
diff --git a/tboot/include/txt/acmod.h b/tboot/include/txt/acmod.h
new file mode 100644
index 0000000..33f8b28
--- /dev/null
+++ b/tboot/include/txt/acmod.h
@@ -0,0 +1,195 @@
+/*
+ * acmod.c: support functions for use of Intel(r) TXT Authenticated
+ * Code (AC) Modules
+ *
+ * Copyright (c) 2003-2011, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __TXT_ACMOD_H__
+#define __TXT_ACMOD_H__
+
+/*
+ * authenticated code (AC) module header (ver 0.0)
+ */
+
+typedef union {
+ uint16_t _raw;
+ struct {
+ uint16_t reserved : 14;
+ uint16_t pre_production : 1;
+ uint16_t debug_signed : 1;
+ };
+} acm_flags_t;
+
+typedef struct {
+ uint16_t module_type;
+ uint16_t module_subtype;
+ uint32_t header_len;
+ uint32_t header_ver; /* currently 0.0 */
+ uint16_t chipset_id;
+ acm_flags_t flags;
+ uint32_t module_vendor;
+ uint32_t date;
+ uint32_t size;
+ uint16_t txt_svn;
+ uint16_t se_svn;
+ uint32_t code_control;
+ uint32_t error_entry_point;
+ uint32_t gdt_limit;
+ uint32_t gdt_base;
+ uint32_t seg_sel;
+ uint32_t entry_point;
+ uint8_t reserved2[64];
+ uint32_t key_size;
+ uint32_t scratch_size;
+ uint8_t rsa2048_pubkey[256];
+ uint32_t pub_exp;
+ uint8_t rsa2048_sig[256];
+ uint32_t scratch[143];//
+ uint8_t user_area[];
+} acm_hdr_t;
+
+/* value of module_type field */
+#define ACM_TYPE_CHIPSET 0x02
+
+/* value of module_subtype field */
+#define ACM_SUBTYPE_RESET 0x01
+
+/* value of module_vendor field */
+#define ACM_VENDOR_INTEL 0x8086
+
+typedef union {
+ uint32_t _raw;
+ struct {
+ uint32_t ext_policy : 2;
+ uint32_t tpm_family : 4;
+ uint32_t tpm_nv_index_set : 1;
+ uint32_t reserved : 25;
+ };
+} tpm_cap_t;
+
+/* ext_policy field values */
+#define TPM_EXT_POLICY_ILLEGAL 0x00
+#define TPM_EXT_POLICY_ALG_AGILE_CMD 0x01
+#define TPM_EXT_POLICY_EMBEDED_ALGS 0x10
+#define TPM_EXT_POLICY_BOTH 0x11
+
+/* tpm_family field values */
+#define TPM_FAMILY_ILLEGAL 0x0000
+#define TPM_FAMILY_DTPM_12 0x0001
+#define TPM_FAMILY_DTPM_20 0x0010
+#define TPM_FAMILY_DTPM_BOTH 0x0011
+#define TPM_FAMILY_PTT_20 0x1000
+
+typedef struct {
+ tpm_cap_t capabilities;
+ uint16_t count;
+ uint16_t alg_id[];
+} tpm_info_list_t;
+
+typedef struct __packed {
+ uuid_t uuid;
+ uint8_t chipset_acm_type;
+ uint8_t version; /* currently 4 */
+ uint16_t length;
+ uint32_t chipset_id_list;
+ uint32_t os_sinit_data_ver;
+ uint32_t min_mle_hdr_ver;
+ txt_caps_t capabilities;
+ uint8_t acm_ver;
+ uint8_t reserved[3];
+ /* versions >= 4 */
+ uint32_t processor_id_list;
+ /* versions >= 5 */
+ uint32_t tpm_info_list_off;
+} acm_info_table_t;
+
+/* ACM UUID value */
+#define ACM_UUID_V3 {0x7fc03aaa, 0x46a7, 0x18db, 0xac2e, \
+ {0x69, 0x8f, 0x8d, 0x41, 0x7f, 0x5a}}
+
+/* chipset_acm_type field values */
+#define ACM_CHIPSET_TYPE_BIOS 0x00
+#define ACM_CHIPSET_TYPE_SINIT 0x01
+#define ACM_CHIPSET_TYPE_BIOS_REVOC 0x08
+#define ACM_CHIPSET_TYPE_SINIT_REVOC 0x09
+
+typedef struct __packed {
+ uint32_t flags;
+ uint16_t vendor_id;
+ uint16_t device_id;
+ uint16_t revision_id;
+ uint16_t reserved;
+ uint32_t extended_id;
+} acm_chipset_id_t;
+
+typedef struct __packed {
+ uint32_t count;
+ acm_chipset_id_t chipset_ids[];
+} acm_chipset_id_list_t;
+
+typedef struct __packed {
+ uint32_t fms;
+ uint32_t fms_mask;
+ uint64_t platform_id;
+ uint64_t platform_mask;
+} acm_processor_id_t;
+
+typedef struct __packed {
+ uint32_t count;
+ acm_processor_id_t processor_ids[];
+} acm_processor_id_list_t;
+
+acm_hdr_t *g_sinit;
+
+void print_txt_caps(const char *prefix, txt_caps_t caps);
+bool is_racm_acmod(const void *acmod_base, uint32_t acmod_size, bool quiet);
+acm_hdr_t *copy_racm(const acm_hdr_t *racm);
+bool verify_racm(const acm_hdr_t *acm_hdr);
+bool is_sinit_acmod(const void *acmod_base, uint32_t acmod_size, bool quiet);
+bool does_acmod_match_platform(const acm_hdr_t* hdr);
+acm_hdr_t *copy_sinit(const acm_hdr_t *sinit);
+bool verify_acmod(const acm_hdr_t *acm_hdr);
+uint32_t get_supported_os_sinit_data_ver(const acm_hdr_t* hdr);
+txt_caps_t get_sinit_capabilities(const acm_hdr_t* hdr);
+tpm_info_list_t *get_tpm_info_list(const acm_hdr_t* hdr);
+void verify_IA32_se_svn_status(const acm_hdr_t *acm_hdr);
+#endif /* __TXT_ACMOD_H__ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/tboot/include/txt/config_regs.h b/tboot/include/txt/config_regs.h
new file mode 100644
index 0000000..4d02ea4
--- /dev/null
+++ b/tboot/include/txt/config_regs.h
@@ -0,0 +1,240 @@
+/*
+ * config_regs.h: Intel(r) TXT configuration register -related definitions
+ *
+ * Copyright (c) 2003-2011, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __TXT_CONFIG_REGS_H__
+#define __TXT_CONFIG_REGS_H__
+
+/*
+ * TXT configuration registers (offsets from TXT_{PUB, PRIV}_CONFIG_REGS_BASE)
+ */
+
+#define TXT_PUB_CONFIG_REGS_BASE 0xfed30000
+#define TXT_PRIV_CONFIG_REGS_BASE 0xfed20000
+
+#define TXT_CONFIG_REGS_SIZE (TXT_PUB_CONFIG_REGS_BASE - \
+ TXT_PRIV_CONFIG_REGS_BASE)
+
+/* offsets to config regs (from either public or private _BASE) */
+#define TXTCR_STS 0x0000
+#define TXTCR_ESTS 0x0008
+#define TXTCR_ERRORCODE 0x0030
+#define TXTCR_CMD_RESET 0x0038
+#define TXTCR_CMD_CLOSE_PRIVATE 0x0048
+#define TXTCR_VER_FSBIF 0x0100
+#define TXTCR_DIDVID 0x0110
+#define TXTCR_VER_QPIIF 0x0200
+#define TXTCR_CMD_UNLOCK_MEM_CONFIG 0x0218
+#define TXTCR_SINIT_BASE 0x0270
+#define TXTCR_SINIT_SIZE 0x0278
+#define TXTCR_MLE_JOIN 0x0290
+#define TXTCR_HEAP_BASE 0x0300
+#define TXTCR_HEAP_SIZE 0x0308
+#define TXTCR_MSEG_BASE 0x0310
+#define TXTCR_MSEG_SIZE 0x0318
+#define TXTCR_DPR 0x0330
+#define TXTCR_CMD_OPEN_LOCALITY1 0x0380
+#define TXTCR_CMD_CLOSE_LOCALITY1 0x0388
+#define TXTCR_CMD_OPEN_LOCALITY2 0x0390
+#define TXTCR_CMD_CLOSE_LOCALITY2 0x0398
+#define TXTCR_PUBLIC_KEY 0x0400
+#define TXTCR_CMD_SECRETS 0x08e0
+#define TXTCR_CMD_NO_SECRETS 0x08e8
+#define TXTCR_E2STS 0x08f0
+
+/*
+ * format of ERRORCODE register
+ */
+typedef union {
+ uint64_t _raw;
+ struct {
+ uint64_t type : 30; /* external-specific error code */
+ uint64_t external : 1; /* 0=from proc, 1=from external SW */
+ uint64_t valid : 1; /* 1=valid */
+ };
+} txt_errorcode_t;
+
+/*
+ * format of ESTS register
+ */
+typedef union {
+ uint64_t _raw;
+ struct {
+ uint64_t txt_reset_sts : 1;
+ };
+} txt_ests_t;
+
+/*
+ * format of E2STS register
+ */
+typedef union {
+ uint64_t _raw;
+ struct {
+ uint64_t reserved : 1;
+ uint64_t secrets_sts : 1;
+ };
+} txt_e2sts_t;
+
+/*
+ * format of STS register
+ */
+typedef union {
+ uint64_t _raw;
+ struct {
+ uint64_t senter_done_sts : 1;
+ uint64_t sexit_done_sts : 1;
+ uint64_t reserved1 : 4;
+ uint64_t mem_config_lock_sts : 1;
+ uint64_t private_open_sts : 1;
+ uint64_t reserved2 : 7;
+ uint64_t locality_1_open_sts : 1;
+ uint64_t locality_2_open_sts : 1;
+ };
+} txt_sts_t;
+
+/*
+ * format of DIDVID register
+ */
+typedef union {
+ uint64_t _raw;
+ struct {
+ uint16_t vendor_id;
+ uint16_t device_id;
+ uint16_t revision_id;
+ uint16_t reserved;
+ };
+} txt_didvid_t;
+
+/*
+ * format of VER.FSBIF and VER.QPIIF registers
+ */
+typedef union {
+ uint64_t _raw;
+ struct {
+ uint64_t reserved : 31;
+ uint64_t prod_fused : 1;
+ };
+} txt_ver_fsbif_qpiif_t;
+
+/*
+ * format of DPR register
+ */
+typedef union {
+ uint64_t _raw;
+ struct {
+ uint64_t lock : 1;
+ uint64_t reserved1 : 3;
+ uint64_t size : 8;
+ uint64_t reserved2 : 8;
+ uint64_t top : 12;
+ uint64_t reserved3 : 32;
+ };
+} txt_dpr_t;
+
+/*
+ * RLP JOIN structure for GETSEC[WAKEUP] and MLE_JOIN register
+ */
+typedef struct {
+ uint32_t gdt_limit;
+ uint32_t gdt_base;
+ uint32_t seg_sel; /* cs (ds, es, ss are seg_sel+8) */
+ uint32_t entry_point; /* phys addr */
+} mle_join_t;
+
+/*
+ * format of MSEG header
+ */
+typedef struct {
+ uint32_t revision_id;
+ uint32_t smm_mon_feat;
+ uint32_t gdtr_limit;
+ uint32_t gdtr_base_offset;
+ uint32_t cs_sel;
+ uint32_t eip_offset;
+ uint32_t esp_offset;
+ uint32_t cr3_offset;
+} mseg_hdr_t;
+
+/* TODO these are causing warnings - changed to ull */
+
+/*
+ * fns to read/write TXT config regs
+ */
+
+#ifndef IS_INCLUDED
+static inline uint64_t read_config_reg(uint64_t config_regs_base, uint32_t reg)
+{
+ /* these are MMIO so make sure compiler doesn't optimize */
+ return *(volatile uint64_t *)(unsigned long long)(config_regs_base + reg);
+}
+#endif
+
+static inline void write_config_reg(uint64_t config_regs_base, uint32_t reg,
+ uint64_t val)
+{
+ /* these are MMIO so make sure compiler doesn't optimize */
+ *(volatile uint64_t *)(unsigned long long)(config_regs_base + reg) = val;
+}
+
+static inline uint64_t read_pub_config_reg(uint32_t reg)
+{
+ return read_config_reg(TXT_PUB_CONFIG_REGS_BASE, reg);
+}
+
+static inline void write_pub_config_reg(uint32_t reg, uint64_t val)
+{
+ write_config_reg(TXT_PUB_CONFIG_REGS_BASE, reg, val);
+}
+
+static inline uint64_t read_priv_config_reg(uint32_t reg)
+{
+ return read_config_reg(TXT_PRIV_CONFIG_REGS_BASE, reg);
+}
+
+static inline void write_priv_config_reg(uint32_t reg, uint64_t val)
+{
+ write_config_reg(TXT_PRIV_CONFIG_REGS_BASE, reg, val);
+}
+
+#endif /* __TXT_CONFIG_REGS_H__ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-set-style: "BSD"
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/tboot/include/txt/errorcode.h b/tboot/include/txt/errorcode.h
new file mode 100644
index 0000000..fe85a3c
--- /dev/null
+++ b/tboot/include/txt/errorcode.h
@@ -0,0 +1,105 @@
+/*
+ * errorcode.h: Intel(r) TXT error definitions for ERRORCODE config register
+ *
+ * Copyright (c) 2003-2011, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __TXT_ERRORCODE_H__
+#define __TXT_ERRORCODE_H__
+
+/*
+ * error values for processor error codes (ERRORCODE.external = 0)
+ */
+#define TXT_ERR_PROC_LEGACY_SHUTDOWN 0
+#define TXT_ERR_PROC_INVALID_ACM_MEM_TYPE 5
+#define TXT_ERR_PROC_UNSUPPORTED_ACM 6
+#define TXT_ERR_PROC_AUTH_FAIL 7
+#define TXT_ERR_PROC_INVALID_ACM_FORMAT 8
+#define TXT_ERR_PROC_UNEXPECTED_HITM 9
+#define TXT_ERR_PROC_INVALID_EVENT 10
+#define TXT_ERR_PROC_INVALID_JOIN_FORMAT 11
+#define TXT_ERR_PROC_UNRECOVERABLE_MCE 12
+#define TXT_ERR_PROC_VMX_ABORT 13
+#define TXT_ERR_PROC_ACM_CORRUPT 14
+#define TXT_ERR_PROC_INVALID_VIDB_RATIO 15
+
+/*
+ * for SW errors (ERRORCODE.external = 1)
+ */
+typedef union {
+ uint32_t _raw;
+ struct {
+ uint32_t err1 : 15; /* specific to src */
+ uint32_t src : 1; /* 0=ACM, 1=other */
+ uint32_t err2 : 14; /* specific to src */
+ uint32_t external : 1; /* always 1 for this type */
+ uint32_t valid : 1; /* always 1 */
+ };
+} txt_errorcode_sw_t;
+
+/*
+ * ACM errors (txt_errorcode_sw_t.src=0), format of err1+src+err2 fields
+ */
+typedef union __attribute__((packed)){
+ uint32_t _raw;
+ struct __attribute__((packed)){
+ uint32_t acm_type : 4; /* 0000=BIOS ACM, 0001=SINIT, */
+ /* 0010-1111=reserved */
+ uint32_t progress : 6;
+ uint32_t error : 5;
+ uint32_t src : 1; /* above value */
+ union __attribute__((packed)){
+ struct __attribute__((packed)) { /* progress=0x0d, error=1010 */
+ uint32_t tpm_err : 9;
+ uint32_t reserved1 : 5;
+ };
+ struct __attribute__((packed)) { /* progress=0x10 */
+ uint32_t lcp_minor : 6;
+ uint32_t lcp_index : 3;
+ uint32_t reserved2 : 5;
+ };
+ }; /* sub-error */
+ };
+} acmod_error_t;
+
+#endif /* __TXT_ERRORCODE_H__ */
+
+
+/*
+ * Local variables:
+ * mode: C
+ * c-set-style: "BSD"
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/tboot/include/txt/heap.h b/tboot/include/txt/heap.h
new file mode 100644
index 0000000..c4e2d51
--- /dev/null
+++ b/tboot/include/txt/heap.h
@@ -0,0 +1,377 @@
+/*
+ * heap.h: Intel(r) TXT heap definitions
+ *
+ * Copyright (c) 2003-2011, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __TXT_HEAP_H__
+#define __TXT_HEAP_H__
+
+/*
+ * Extensible TXT heap data structure
+ */
+
+typedef struct __packed {
+ uint32_t type;
+ uint32_t size;
+ uint8_t data[];
+} heap_ext_data_element_t;
+
+/*
+ * HEAP_END_ELEMENT
+ */
+#define HEAP_EXTDATA_TYPE_END 0
+
+/* size == 8; there is no data[] */
+
+/*
+ * HEAP_BIOS_SPEC_VER_ELEMENT
+ */
+#define HEAP_EXTDATA_TYPE_BIOS_SPEC_VER 1
+
+typedef struct __packed {
+ uint16_t spec_ver_major;
+ uint16_t spec_ver_minor;
+ uint16_t spec_ver_rev;
+} heap_bios_spec_ver_elt_t;
+
+/*
+ * HEAP_ACM_ELEMENT
+ */
+#define HEAP_EXTDATA_TYPE_ACM 2
+
+typedef struct __packed {
+ uint32_t num_acms;
+ uint64_t acm_addrs[];
+} heap_acm_elt_t;
+
+/*
+ * HEAP_CUSTOM_ELEMENT
+ */
+#define HEAP_EXTDATA_TYPE_CUSTOM 4
+
+typedef struct __packed {
+ uuid_t uuid;
+ uint8_t data[];
+} heap_custom_elt_t;
+
+/*
+ * HEAP_EVENT_LOG_POINTER_ELEMENT
+ */
+#define HEAP_EXTDATA_TYPE_TPM_EVENT_LOG_PTR 5
+
+typedef struct __packed {
+ uint64_t event_log_phys_addr;
+} heap_event_log_ptr_elt_t;
+
+typedef struct __packed {
+ uint32_t pcr_index;
+ uint32_t type;
+ sha1_hash_t digest;
+ uint32_t data_size;
+ uint8_t data[];
+} tpm12_pcr_event_t;
+
+#define EVTLOG_SIGNATURE "TXT Event Container\0"
+#define EVTLOG_CNTNR_MAJOR_VER 1
+#define EVTLOG_CNTNR_MINOR_VER 0
+#define EVTLOG_EVT_MAJOR_VER 1
+#define EVTLOG_EVT_MINOR_VER 0
+typedef struct __packed {
+ uint8_t signature[20];
+ uint8_t reserved[12];
+ uint8_t container_ver_major;
+ uint8_t container_ver_minor;
+ uint8_t pcr_event_ver_major;
+ uint8_t pcr_event_ver_minor;
+ uint32_t size;
+ uint32_t pcr_events_offset;
+ uint32_t next_event_offset;
+ tpm12_pcr_event_t pcr_events[];
+} event_log_container_t;
+
+/*
+ * HEAP_EVENT_LOG_POINTER_ELEMENT2
+ */
+#define HEAP_EXTDATA_TYPE_TPM_EVENT_LOG_PTR_2 7
+
+#define DIGEST_ALG_ID_SHA_1 0x00000001
+#define DIGEST_ALG_ID_SHA_256 0x00000002
+#define DIGEST_ALG_ID_SHA_384 0x00000003
+#define DIGEST_ALG_ID_SHA_512 0x00000004
+#define DIGEST_ALG_ID_SM3 0x00000005
+static inline unsigned int get_evtlog_digest_id(uint16_t hash_alg)
+{
+ if ( hash_alg == TB_HALG_SHA1 )
+ return DIGEST_ALG_ID_SHA_1;
+ else if ( hash_alg == TB_HALG_SHA256 )
+ return DIGEST_ALG_ID_SHA_256;
+ else if ( hash_alg == TB_HALG_SM3 )
+ return DIGEST_ALG_ID_SM3;
+ else if ( hash_alg == TB_HALG_SHA384 )
+ return DIGEST_ALG_ID_SHA_384;
+ else if ( hash_alg == TB_HALG_SHA512 )
+ return DIGEST_ALG_ID_SHA_512;
+ else
+ return 0;
+}
+
+typedef struct __packed {
+ uint8_t signature[16];
+ uint32_t revision;
+ uint32_t digest_id;
+ uint32_t digest_size;
+} tpm20_log_descr_t;
+
+typedef struct __packed {
+ uint16_t alg;
+ uint16_t reserved;
+ uint64_t phys_addr;
+ uint32_t size;
+ uint32_t pcr_events_offset;
+ uint32_t next_event_offset;
+} heap_event_log_descr_t;
+
+typedef struct __packed {
+ uint32_t count;
+ heap_event_log_descr_t event_log_descr[];
+} heap_event_log_ptr_elt2_t;
+
+
+/*
+ * data-passing structures contained in TXT heap:
+ * - BIOS
+ * - OS/loader to MLE
+ * - OS/loader to SINIT
+ * - SINIT to MLE
+ */
+
+/*
+ * BIOS structure
+ */
+typedef struct __packed {
+ uint32_t version; /* currently 2-4 */
+ uint32_t bios_sinit_size;
+ uint64_t lcp_pd_base;
+ uint64_t lcp_pd_size;
+ uint32_t num_logical_procs;
+ /* versions >= 3 */
+ uint64_t flags; /* For TPM2, it is divided into sinit_flag and mle_flag */
+ /* versions >= 4 */
+ heap_ext_data_element_t ext_data_elts[];
+} bios_data_t;
+
+/*
+ * OS/loader to MLE structure
+ * - private to tboot (so can be any format we need)
+ */
+#define MAX_LCP_PO_DATA_SIZE 64*1024 /* 64k */
+#define MAX_EVENT_LOG_SIZE 5*4*1024 /* 4k*5 */
+
+typedef struct __packed {
+ uint32_t version; /* currently 3 */
+ mtrr_state_t saved_mtrr_state; /* saved prior to changes for SINIT */
+ uint64_t saved_misc_enable_msr; /* saved prior to SENTER */
+ /* PO policy data */
+ uint8_t lcp_po_data[MAX_LCP_PO_DATA_SIZE];
+ /* buffer for tpm event log */
+ uint8_t event_log_buffer[MAX_EVENT_LOG_SIZE];
+} os_mle_data_t;
+
+#define MIN_OS_SINIT_DATA_VER 4
+#define MAX_OS_SINIT_DATA_VER 7
+#define OS_SINIT_FLAGS_EXTPOL_MASK 0x00000001
+/*
+ * OS/loader to SINIT structure
+ */
+typedef struct __packed {
+ uint32_t version; /* currently 4-7 */
+ uint32_t flags; /* For TPM2: BIT0:= PCR Extend Policy Control */
+ uint64_t mle_ptab;
+ uint64_t mle_size;
+ uint64_t mle_hdr_base;
+ uint64_t vtd_pmr_lo_base;
+ uint64_t vtd_pmr_lo_size;
+ uint64_t vtd_pmr_hi_base;
+ uint64_t vtd_pmr_hi_size;
+ uint64_t lcp_po_base;
+ uint64_t lcp_po_size;
+ txt_caps_t capabilities;
+ /* versions >= 5 */
+ uint64_t efi_rsdt_ptr;
+ /* versions >= 6 */
+ heap_ext_data_element_t ext_data_elts[];
+} os_sinit_data_t;
+
+/*
+ * SINIT to MLE structure
+ */
+#define MDR_MEMTYPE_GOOD 0x00
+#define MDR_MEMTYPE_SMM_OVERLAY 0x01
+#define MDR_MEMTYPE_SMM_NONOVERLAY 0x02
+#define MDR_MEMTYPE_PCIE_CONFIG_SPACE 0x03
+#define MDR_MEMTYPE_PROTECTED 0x04
+
+typedef struct __packed {
+ uint64_t base;
+ uint64_t length;
+ uint8_t mem_type;
+ uint8_t reserved[7];
+} sinit_mdr_t;
+
+typedef struct __packed {
+ uint32_t version; /* currently 6-9 */
+ sha1_hash_t bios_acm_id; /* only for tpm1.2 */
+ uint32_t edx_senter_flags; /* only for tpm1.2 */
+ uint64_t mseg_valid; /* only for tpm1.2 */
+ sha1_hash_t sinit_hash; /* only for tpm1.2 */
+ sha1_hash_t mle_hash; /* only for tpm1.2 */
+ sha1_hash_t stm_hash; /* only for tpm1.2 */
+ sha1_hash_t lcp_policy_hash; /* only for tpm1.2 */
+ uint32_t lcp_policy_control; /* only for tpm1.2 */
+ uint32_t rlp_wakeup_addr;
+ uint32_t reserved;
+ uint32_t num_mdrs;
+ uint32_t mdrs_off;
+ uint32_t num_vtd_dmars;
+ uint32_t vtd_dmars_off;
+ /* versions >= 8 */
+ uint32_t proc_scrtm_status; /* only for tpm1.2 */
+ /* versions >= 9 */
+ heap_ext_data_element_t ext_data_elts[];
+} sinit_mle_data_t;
+
+
+/*
+ * TXT heap data format and field accessor fns
+ */
+
+/*
+ * offset length field
+ * ------ ------ -----
+ * 0 8 bios_data_size
+ * 8 bios_data_size - 8 bios_data
+ *
+ * bios_data_size 8 os_mle_data_size
+ * bios_data_size + os_mle_data_size - 8 os_mle_data
+ * 8
+ *
+ * bios_data_size + 8 os_sinit_data_size
+ * os_mle_data_size
+ * bios_data_size + os_sinit_data_size - 8 os_sinit_data
+ * os_mle_data_size +
+ * 8
+ *
+ * bios_data_size + 8 sinit_mle_data_size
+ * os_mle_data_size +
+ * os_sinit_data_size
+ * bios_data_size + sinit_mle_data_size - 8 sinit_mle_data
+ * os_mle_data_size +
+ * os_sinit_data_size +
+ * 8
+ */
+
+typedef void txt_heap_t;
+
+/* TODO these are causing warnings - changed to ull */
+
+/* this is a common use with annoying casting, so make it an inline */
+static inline txt_heap_t *get_txt_heap(void)
+{
+ return (txt_heap_t *)(unsigned long long)read_pub_config_reg(TXTCR_HEAP_BASE);
+}
+
+static inline uint64_t get_bios_data_size(const txt_heap_t *heap)
+{
+ return *(uint64_t *)heap;
+}
+
+static inline bios_data_t *get_bios_data_start(const txt_heap_t *heap)
+{
+ return (bios_data_t *)((char*)heap + sizeof(uint64_t));
+}
+
+static inline uint64_t get_os_mle_data_size(const txt_heap_t *heap)
+{
+ return *(uint64_t *)(heap + get_bios_data_size(heap));
+}
+
+static inline os_mle_data_t *get_os_mle_data_start(const txt_heap_t *heap)
+{
+ return (os_mle_data_t *)(heap + get_bios_data_size(heap) +
+ sizeof(uint64_t));
+}
+
+static inline uint64_t get_os_sinit_data_size(const txt_heap_t *heap)
+{
+ return *(uint64_t *)(heap + get_bios_data_size(heap) +
+ get_os_mle_data_size(heap));
+}
+
+static inline os_sinit_data_t *get_os_sinit_data_start(const txt_heap_t *heap)
+{
+ return (os_sinit_data_t *)(heap + get_bios_data_size(heap) +
+ get_os_mle_data_size(heap) +
+ sizeof(uint64_t));
+}
+
+static inline uint64_t get_sinit_mle_data_size(const txt_heap_t *heap)
+{
+ return *(uint64_t *)(heap + get_bios_data_size(heap) +
+ get_os_mle_data_size(heap) +
+ get_os_sinit_data_size(heap));
+}
+
+static inline sinit_mle_data_t *get_sinit_mle_data_start(const txt_heap_t *heap)
+{
+ return (sinit_mle_data_t *)(heap + get_bios_data_size(heap) +
+ get_os_mle_data_size(heap) +
+ get_os_sinit_data_size(heap) +
+ sizeof(uint64_t));
+}
+
+uint64_t calc_os_sinit_data_size(uint32_t version);
+bool verify_txt_heap(const txt_heap_t *txt_heap, bool bios_data_only);
+bool verify_bios_data(const txt_heap_t *txt_heap);
+void print_os_sinit_data(const os_sinit_data_t *os_sinit_data);
+
+#endif /* __TXT_HEAP_H__ */
+
+
+/*
+ * Local variables:
+ * mode: C
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/tboot/include/txt/mtrrs.h b/tboot/include/txt/mtrrs.h
new file mode 100644
index 0000000..8b61f6e
--- /dev/null
+++ b/tboot/include/txt/mtrrs.h
@@ -0,0 +1,149 @@
+/*
+ * mtrrs.c: Intel(r) TXT MTRR-related definitions
+ *
+ * Copyright (c) 2003-2010, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __TXT_MTRRS_H__
+#define __TXT_MTRRS_H__
+
+#include <txt/acmod.h>
+
+enum fix_mtrr_t {
+ MTRR_FIX64K_00000 = 0x250,
+ MTRR_FIX16K_80000 = 0x258,
+ MTRR_FIX16K_A0000 = 0x259,
+ MTRR_FIX4K_C0000 = 0x268,
+ MTRR_FIX4K_C8000 = 0x269,
+ MTRR_FIX4K_D0000 = 0x26A,
+ MTRR_FIX4K_D8000 = 0x26B,
+ MTRR_FIX4K_E0000 = 0x26C,
+ MTRR_FIX4K_E8000 = 0x26D,
+ MTRR_FIX4K_F0000 = 0x26E,
+ MTRR_FIX4K_F8000 = 0x26F
+};
+
+typedef union {
+ uint64_t raw;
+ uint8_t type[8];
+} mtrr_fix_types_t;
+
+enum var_mtrr_t {
+ MTRR_PHYS_BASE0_MSR = 0x200,
+ MTRR_PHYS_MASK0_MSR = 0x201,
+ MTRR_PHYS_BASE1_MSR = 0x202,
+ MTRR_PHYS_MASK1_MSR = 0x203,
+ MTRR_PHYS_BASE2_MSR = 0x204,
+ MTRR_PHYS_MASK2_MSR = 0x205,
+ MTRR_PHYS_BASE3_MSR = 0x206,
+ MTRR_PHYS_MASK3_MSR = 0x207,
+ MTRR_PHYS_BASE4_MSR = 0x208,
+ MTRR_PHYS_MASK4_MSR = 0x209,
+ MTRR_PHYS_BASE5_MSR = 0x20A,
+ MTRR_PHYS_MASK5_MSR = 0x20B,
+ MTRR_PHYS_BASE6_MSR = 0x20C,
+ MTRR_PHYS_MASK6_MSR = 0x20D,
+ MTRR_PHYS_BASE7_MSR = 0x20E,
+ MTRR_PHYS_MASK7_MSR = 0x20F
+};
+
+typedef union {
+ uint64_t raw;
+ struct {
+ uint64_t vcnt : 8; /* num variable MTRR pairs */
+ uint64_t fix : 1; /* fixed range MTRRs are supported */
+ uint64_t reserved1 : 1;
+ uint64_t wc : 1; /* write-combining mem type supported */
+ uint64_t reserved2 : 53;
+ };
+} mtrr_cap_t;
+
+typedef union {
+ uint64_t raw;
+ struct {
+ uint64_t type : 8;
+ uint64_t reserved1 : 2;
+ uint64_t fe : 1; /* fixed MTRR enable */
+ uint64_t e : 1; /* (all) MTRR enable */
+ uint64_t reserved2 : 52;
+ };
+} mtrr_def_type_t;
+
+typedef union {
+ uint64_t raw;
+ struct {
+ uint64_t type : 8;
+ uint64_t reserved1 : 4;
+ uint64_t base : 52; /* define as max width and mask w/ */
+ /* MAXPHYADDR when using */
+ };
+} mtrr_physbase_t;
+
+typedef union {
+ uint64_t raw;
+ struct {
+ uint64_t reserved1 : 11;
+ uint64_t v : 1; /* valid */
+ uint64_t mask : 52; /* define as max width and mask w/ */
+ /* MAXPHYADDR when using */
+ };
+} mtrr_physmask_t;
+
+/* current procs only have 8, so this should hold us for a while */
+#define MAX_VARIABLE_MTRRS 16
+
+typedef struct {
+ mtrr_def_type_t mtrr_def_type;
+ unsigned int num_var_mtrrs;
+ mtrr_physbase_t mtrr_physbases[MAX_VARIABLE_MTRRS];
+ mtrr_physmask_t mtrr_physmasks[MAX_VARIABLE_MTRRS];
+} mtrr_state_t;
+
+bool set_mtrrs_for_acmod(const acm_hdr_t *hdr);
+void save_mtrrs(mtrr_state_t *saved_state);
+void set_all_mtrrs(bool enable);
+bool set_mem_type(const void *base, uint32_t size, uint32_t mem_type);
+void restore_mtrrs(const mtrr_state_t *saved_state);
+bool validate_mtrrs(const mtrr_state_t *saved_state);
+
+#endif /*__TXT_MTRRS_H__ */
+
+
+/*
+ * Local variables:
+ * mode: C
+ * c-set-style: "BSD"
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/tboot/include/txt/smx.h b/tboot/include/txt/smx.h
new file mode 100644
index 0000000..93645c7
--- /dev/null
+++ b/tboot/include/txt/smx.h
@@ -0,0 +1,171 @@
+/*
+ * smx.h: Intel(r) TXT SMX architecture-related definitions
+ *
+ * Copyright (c) 2003-2008, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __TXT_SMX_H__
+#define __TXT_SMX_H__
+
+/*
+ * GETSEC[] instructions
+ */
+
+/* GETSEC instruction opcode */
+#define IA32_GETSEC_OPCODE ".byte 0x0f,0x37"
+
+/* GETSEC leaf function codes */
+#define IA32_GETSEC_CAPABILITIES 0
+#define IA32_GETSEC_ENTERACCS 2
+#define IA32_GETSEC_SENTER 4
+#define IA32_GETSEC_SEXIT 5
+#define IA32_GETSEC_PARAMETERS 6
+#define IA32_GETSEC_SMCTRL 7
+#define IA32_GETSEC_WAKEUP 8
+
+/*
+ * GETSEC[] leaf functions
+ */
+
+typedef union {
+ uint32_t _raw;
+ struct {
+ uint32_t chipset_present : 1;
+ uint32_t undefined1 : 1;
+ uint32_t enteraccs : 1;
+ uint32_t exitac : 1;
+ uint32_t senter : 1;
+ uint32_t sexit : 1;
+ uint32_t parameters : 1;
+ uint32_t smctrl : 1;
+ uint32_t wakeup : 1;
+ uint32_t undefined9 : 22;
+ uint32_t extended_leafs : 1;
+ };
+} capabilities_t;
+
+static inline capabilities_t __getsec_capabilities(uint32_t index)
+{
+ uint32_t cap;
+ __asm__ __volatile__ (IA32_GETSEC_OPCODE "\n"
+ : "=a"(cap)
+ : "a"(IA32_GETSEC_CAPABILITIES), "b"(index));
+ return (capabilities_t)cap;
+}
+
+/* helper fn. for getsec_capabilities */
+/* this is arbitrary and can be increased when needed */
+#define MAX_SUPPORTED_ACM_VERSIONS 16
+
+typedef struct {
+ struct {
+ uint32_t mask;
+ uint32_t version;
+ } acm_versions[MAX_SUPPORTED_ACM_VERSIONS];
+ int n_versions;
+ uint32_t acm_max_size;
+ uint32_t acm_mem_types;
+ uint32_t senter_controls;
+ bool proc_based_scrtm;
+ bool preserve_mce;
+} getsec_parameters_t;
+
+bool get_parameters(getsec_parameters_t *params);
+
+
+static inline void __getsec_senter(uint32_t sinit_base, uint32_t sinit_size)
+{
+ __asm__ __volatile__ (IA32_GETSEC_OPCODE "\n"
+ :
+ : "a"(IA32_GETSEC_SENTER),
+ "b"(sinit_base),
+ "c"(sinit_size),
+ "d"(0x0));
+}
+
+static inline void __getsec_sexit(void)
+{
+ __asm__ __volatile__ (IA32_GETSEC_OPCODE "\n"
+ : : "a"(IA32_GETSEC_SEXIT));
+}
+
+static inline void __getsec_wakeup(void)
+{
+ __asm__ __volatile__ (IA32_GETSEC_OPCODE "\n"
+ : : "a"(IA32_GETSEC_WAKEUP));
+}
+
+static inline void __getsec_smctrl(void)
+{
+ __asm__ __volatile__ (IA32_GETSEC_OPCODE "\n"
+ : : "a"(IA32_GETSEC_SMCTRL), "b"(0x0));
+}
+
+static inline void __getsec_parameters(uint32_t index, int* param_type,
+ uint32_t* peax, uint32_t* pebx,
+ uint32_t* pecx)
+{
+ uint32_t eax=0, ebx=0, ecx=0;
+ __asm__ __volatile__ (IA32_GETSEC_OPCODE "\n"
+ : "=a"(eax), "=b"(ebx), "=c"(ecx)
+ : "a"(IA32_GETSEC_PARAMETERS), "b"(index));
+
+ if ( param_type != NULL ) *param_type = eax & 0x1f;
+ if ( peax != NULL ) *peax = eax;
+ if ( pebx != NULL ) *pebx = ebx;
+ if ( pecx != NULL ) *pecx = ecx;
+}
+
+static inline void __getsec_enteraccs(uint32_t acm_base, uint32_t acm_size,
+ uint32_t fn)
+{
+ __asm__ __volatile__ (IA32_GETSEC_OPCODE "\n"
+ :
+ : "a"(IA32_GETSEC_ENTERACCS),
+ "b"(acm_base),
+ "c"(acm_size),
+ "D"(0),
+ "S"(fn));
+}
+
+
+#endif /* __TXT_SMX_H__ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-set-style: "BSD"
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/tboot/include/txt/txt.h b/tboot/include/txt/txt.h
new file mode 100644
index 0000000..2555e70
--- /dev/null
+++ b/tboot/include/txt/txt.h
@@ -0,0 +1,76 @@
+/*
+ * txt.h: Intel(r) TXT support functions
+ *
+ * Copyright (c) 2003-2008, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __TXT_TXT_H__
+#define __TXT_TXT_H__
+
+// #include <multiboot.h>
+
+void txt_init_mle_header(void);
+bool txt_build_mle_pagetable(void);
+bool txt_is_launched(void);
+bool txt_get_error(void);
+void txt_get_racm_error(void);
+tb_error_t supports_txt(void);
+tb_error_t txt_verify_platform(void);
+bool txt_prepare_cpu(void);
+tb_error_t txt_launch_environment(void);
+/* TODO need to address the loader business, stub out for now
+tb_error_t txt_launch_racm(loader_ctx *lctx);
+*/
+void txt_post_launch(void);
+tb_error_t txt_protect_mem_regions(void);
+tb_error_t txt_post_launch_verify_platform(void);
+bool txt_s3_launch_environment(void);
+void txt_shutdown(void);
+bool txt_is_powercycle_required(void);
+void ap_wait(unsigned int cpuid);
+
+uint32_t g_using_da;
+atomic_t ap_wfs_count;
+
+#endif /* __TXT_TXT_H__ */
+
+
+/*
+ * Local variables:
+ * mode: C
+ * c-set-style: "BSD"
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
+
diff --git a/tboot/include/txt/verify.h b/tboot/include/txt/verify.h
new file mode 100644
index 0000000..659af15
--- /dev/null
+++ b/tboot/include/txt/verify.h
@@ -0,0 +1,57 @@
+/*
+ * verify.h: support functions for platform Intel(r) TXT verification
+ *
+ * Copyright (c) 2003-2008, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __TXT_VERIFY_H__
+#define __TXT_VERIFY_H__
+
+void set_vtd_pmrs(os_sinit_data_t *os_sinit_data,
+ uint64_t min_lo_ram, uint64_t max_lo_ram,
+ uint64_t min_hi_ram, uint64_t max_hi_ram);
+bool verify_e820_map(sinit_mdr_t* mdrs_base, uint32_t num_mdrs);
+bool verify_stm(unsigned int cpuid);
+bool use_mwait(void);
+
+#endif /* __TXT_VERIFY_H__ */
+
+
+/*
+ * Local variables:
+ * mode: C
+ * c-set-style: "BSD"
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/tboot/include/txt/vmcs.h b/tboot/include/txt/vmcs.h
new file mode 100644
index 0000000..74f6ecc
--- /dev/null
+++ b/tboot/include/txt/vmcs.h
@@ -0,0 +1,346 @@
+/*
+ * vmcs.h: VMCS definitions for creation of APs mini-guests
+ *
+ * Copyright (c) 2003-2009, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of the Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __TXT_VMCS_H__
+#define __TXT_VMCS_H__
+
+struct vmcs_struct {
+ uint32_t vmcs_revision_id;
+ unsigned char data[0]; /* vmcs size is read from MSR */
+};
+
+union vmcs_arbytes {
+ struct arbyte_fields {
+ unsigned int seg_type : 4,
+ s : 1,
+ dpl : 2,
+ p : 1,
+ reserved0 : 4,
+ avl : 1,
+ reserved1 : 1,
+ default_ops_size: 1,
+ g : 1,
+ null_bit : 1,
+ reserved2 : 15;
+ } fields;
+ unsigned int bytes;
+};
+
+#define CPU_BASED_HLT_EXITING 0x00000080
+#define CPU_BASED_INVDPG_EXITING 0x00000200
+#define CPU_BASED_MWAIT_EXITING 0x00000400
+
+#define PIN_BASED_EXT_INTR_MASK 0x00000001
+#define PIN_BASED_NMI_EXITING 0x00000008
+
+#define VM_EXIT_IA32E_MODE 0x00000200
+#define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
+
+#define VM_ENTRY_IA32E_MODE 0x00000200
+#define VM_ENTRY_SMM 0x00000400
+#define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
+
+
+/* VMCS Encordings */
+enum vmcs_field {
+ GUEST_ES_SELECTOR = 0x00000800,
+ GUEST_CS_SELECTOR = 0x00000802,
+ GUEST_SS_SELECTOR = 0x00000804,
+ GUEST_DS_SELECTOR = 0x00000806,
+ GUEST_FS_SELECTOR = 0x00000808,
+ GUEST_GS_SELECTOR = 0x0000080a,
+ GUEST_LDTR_SELECTOR = 0x0000080c,
+ GUEST_TR_SELECTOR = 0x0000080e,
+ HOST_ES_SELECTOR = 0x00000c00,
+ HOST_CS_SELECTOR = 0x00000c02,
+ HOST_SS_SELECTOR = 0x00000c04,
+ HOST_DS_SELECTOR = 0x00000c06,
+ HOST_FS_SELECTOR = 0x00000c08,
+ HOST_GS_SELECTOR = 0x00000c0a,
+ HOST_TR_SELECTOR = 0x00000c0c,
+ IO_BITMAP_A = 0x00002000,
+ IO_BITMAP_A_HIGH = 0x00002001,
+ IO_BITMAP_B = 0x00002002,
+ IO_BITMAP_B_HIGH = 0x00002003,
+ VM_EXIT_MSR_STORE_ADDR = 0x00002006,
+ VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
+ VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
+ VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
+ VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
+ VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
+ TSC_OFFSET = 0x00002010,
+ TSC_OFFSET_HIGH = 0x00002011,
+ VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
+ VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
+ VMCS_LINK_POINTER = 0x00002800,
+ VMCS_LINK_POINTER_HIGH = 0x00002801,
+ GUEST_IA32_DEBUGCTL = 0x00002802,
+ GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
+ PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
+ CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
+ EXCEPTION_BITMAP = 0x00004004,
+ PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
+ PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
+ CR3_TARGET_COUNT = 0x0000400a,
+ VM_EXIT_CONTROLS = 0x0000400c,
+ VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
+ VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
+ VM_ENTRY_CONTROLS = 0x00004012,
+ VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
+ VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
+ VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
+ VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
+ TPR_THRESHOLD = 0x0000401c,
+ SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
+ VM_INSTRUCTION_ERROR = 0x00004400,
+ VM_EXIT_REASON = 0x00004402,
+ VM_EXIT_INTR_INFO = 0x00004404,
+ VM_EXIT_INTR_ERROR_CODE = 0x00004406,
+ IDT_VECTORING_INFO_FIELD = 0x00004408,
+ IDT_VECTORING_ERROR_CODE = 0x0000440a,
+ VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
+ VMX_INSTRUCTION_INFO = 0x0000440e,
+ GUEST_ES_LIMIT = 0x00004800,
+ GUEST_CS_LIMIT = 0x00004802,
+ GUEST_SS_LIMIT = 0x00004804,
+ GUEST_DS_LIMIT = 0x00004806,
+ GUEST_FS_LIMIT = 0x00004808,
+ GUEST_GS_LIMIT = 0x0000480a,
+ GUEST_LDTR_LIMIT = 0x0000480c,
+ GUEST_TR_LIMIT = 0x0000480e,
+ GUEST_GDTR_LIMIT = 0x00004810,
+ GUEST_IDTR_LIMIT = 0x00004812,
+ GUEST_ES_AR_BYTES = 0x00004814,
+ GUEST_CS_AR_BYTES = 0x00004816,
+ GUEST_SS_AR_BYTES = 0x00004818,
+ GUEST_DS_AR_BYTES = 0x0000481a,
+ GUEST_FS_AR_BYTES = 0x0000481c,
+ GUEST_GS_AR_BYTES = 0x0000481e,
+ GUEST_LDTR_AR_BYTES = 0x00004820,
+ GUEST_TR_AR_BYTES = 0x00004822,
+ GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
+ GUEST_ACTIVITY_STATE = 0x00004826,
+ GUEST_SYSENTER_CS = 0x0000482A,
+ HOST_IA32_SYSENTER_CS = 0x00004c00,
+ CR0_GUEST_HOST_MASK = 0x00006000,
+ CR4_GUEST_HOST_MASK = 0x00006002,
+ CR0_READ_SHADOW = 0x00006004,
+ CR4_READ_SHADOW = 0x00006006,
+ CR3_TARGET_VALUE0 = 0x00006008,
+ CR3_TARGET_VALUE1 = 0x0000600a,
+ CR3_TARGET_VALUE2 = 0x0000600c,
+ CR3_TARGET_VALUE3 = 0x0000600e,
+ EXIT_QUALIFICATION = 0x00006400,
+ GUEST_LINEAR_ADDRESS = 0x0000640a,
+ GUEST_CR0 = 0x00006800,
+ GUEST_CR3 = 0x00006802,
+ GUEST_CR4 = 0x00006804,
+ GUEST_ES_BASE = 0x00006806,
+ GUEST_CS_BASE = 0x00006808,
+ GUEST_SS_BASE = 0x0000680a,
+ GUEST_DS_BASE = 0x0000680c,
+ GUEST_FS_BASE = 0x0000680e,
+ GUEST_GS_BASE = 0x00006810,
+ GUEST_LDTR_BASE = 0x00006812,
+ GUEST_TR_BASE = 0x00006814,
+ GUEST_GDTR_BASE = 0x00006816,
+ GUEST_IDTR_BASE = 0x00006818,
+ GUEST_DR7 = 0x0000681a,
+ GUEST_RSP = 0x0000681c,
+ GUEST_RIP = 0x0000681e,
+ GUEST_RFLAGS = 0x00006820,
+ GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
+ GUEST_SYSENTER_ESP = 0x00006824,
+ GUEST_SYSENTER_EIP = 0x00006826,
+ HOST_CR0 = 0x00006c00,
+ HOST_CR3 = 0x00006c02,
+ HOST_CR4 = 0x00006c04,
+ HOST_FS_BASE = 0x00006c06,
+ HOST_GS_BASE = 0x00006c08,
+ HOST_TR_BASE = 0x00006c0a,
+ HOST_GDTR_BASE = 0x00006c0c,
+ HOST_IDTR_BASE = 0x00006c0e,
+ HOST_IA32_SYSENTER_ESP = 0x00006c10,
+ HOST_IA32_SYSENTER_EIP = 0x00006c12,
+ HOST_RSP = 0x00006c14,
+ HOST_RIP = 0x00006c16,
+};
+
+enum guest_activity_state {
+ GUEST_STATE_ACTIVE = 0,
+ GUEST_STATE_HALT = 1,
+ GUEST_STATE_SHUTDOWN = 2,
+ GUEST_STATE_WAIT_SIPI = 3,
+};
+
+#define VMCALL_OPCODE ".byte 0x0f,0x01,0xc1\n"
+#define VMCLEAR_OPCODE ".byte 0x66,0x0f,0xc7\n" /* reg/opcode: /6 */
+#define VMLAUNCH_OPCODE ".byte 0x0f,0x01,0xc2\n"
+#define VMPTRLD_OPCODE ".byte 0x0f,0xc7\n" /* reg/opcode: /6 */
+#define VMPTRST_OPCODE ".byte 0x0f,0xc7\n" /* reg/opcode: /7 */
+#define VMREAD_OPCODE ".byte 0x0f,0x78\n"
+#define VMRESUME_OPCODE ".byte 0x0f,0x01,0xc3\n"
+#define VMWRITE_OPCODE ".byte 0x0f,0x79\n"
+#define VMXOFF_OPCODE ".byte 0x0f,0x01,0xc4\n"
+#define VMXON_OPCODE ".byte 0xf3,0x0f,0xc7\n"
+
+#define MODRM_EAX_06 ".byte 0x30\n" /* [EAX], with reg/opcode: /6 */
+#define MODRM_EAX_07 ".byte 0x38\n" /* [EAX], with reg/opcode: /7 */
+#define MODRM_EAX_ECX ".byte 0xc1\n" /* [EAX], [ECX] */
+
+/*
+ * Exit Reasons
+ */
+#define VMX_EXIT_REASONS_FAILED_VMENTRY 0x80000000
+
+#define EXIT_REASON_INIT 3
+#define EXIT_REASON_SIPI 4
+#define EXIT_REASON_VMCALL 18
+#define EXIT_REASON_INVALID_GUEST_STATE 33
+#define EXIT_REASON_MSR_LOADING 34
+#define EXIT_REASON_MACHINE_CHECK 41
+
+static inline void __vmptrld(uint64_t addr)
+{
+ /* TBD: do not crash on failure */
+ __asm__ __volatile__ ( VMPTRLD_OPCODE
+ MODRM_EAX_06
+ /* CF==1 or ZF==1 --> crash (ud2) */
+ "ja 1f ; ud2 ; 1:\n"
+ :
+ : "a" (&addr)
+ : "memory");
+}
+
+static inline void __vmptrst(uint64_t addr)
+{
+ __asm__ __volatile__ ( VMPTRST_OPCODE
+ MODRM_EAX_07
+ :
+ : "a" (&addr)
+ : "memory");
+}
+
+static inline void __vmpclear(uint64_t addr)
+{
+ /* TBD: do not crash on failure */
+ __asm__ __volatile__ ( VMCLEAR_OPCODE
+ MODRM_EAX_06
+ /* CF==1 or ZF==1 --> crash (ud2) */
+ "ja 1f ; ud2 ; 1:\n"
+ :
+ : "a" (&addr)
+ : "memory");
+}
+
+static inline unsigned long __vmread(unsigned long field)
+{
+ unsigned long ecx;
+
+ /* TBD: do not crash on failure */
+ __asm__ __volatile__ ( VMREAD_OPCODE
+ MODRM_EAX_ECX
+ /* CF==1 or ZF==1 --> crash (ud2) */
+ "ja 1f ; ud2 ; 1:\n"
+ : "=c" (ecx)
+ : "a" (field)
+ : "memory");
+
+ return ecx;
+}
+
+static inline void __vmwrite(unsigned long field, unsigned long value)
+{
+ /* TBD: do not crash on failure */
+ __asm__ __volatile__ ( VMWRITE_OPCODE
+ MODRM_EAX_ECX
+ /* CF==1 or ZF==1 --> crash (ud2) */
+ "ja 1f ; ud2 ; 1:\n"
+ :
+ : "a" (field) , "c" (value)
+ : "memory");
+}
+
+static inline void __vmlaunch (void)
+{
+ __asm__ __volatile__ ( VMLAUNCH_OPCODE
+ ::: "memory");
+}
+
+static inline void __vmresume (void)
+{
+ __asm__ __volatile__ ( VMRESUME_OPCODE
+ ::: "memory");
+}
+
+static inline void __vmxoff (void)
+{
+ __asm__ __volatile__ ( VMXOFF_OPCODE
+ ::: "memory");
+}
+
+static inline int __vmxon (uint64_t addr)
+{
+ int rc;
+
+ __asm__ __volatile__ ( VMXON_OPCODE
+ MODRM_EAX_06
+ /* CF==1 or ZF==1 --> rc = -1 */
+ "setna %b0 ; neg %0"
+ : "=q" (rc)
+ : "0" (0), "a" (&addr)
+ : "memory");
+
+ return rc;
+}
+
+void handle_init_sipi_sipi(unsigned int cpuid);
+void force_aps_exit(void);
+void init_vmcs_addrs(void);
+
+struct mutex ap_lock;
+
+#endif /* __TXT_VMCS_H__ */
+
+
+/*
+ * Local variables:
+ * mode: C
+ * c-set-style: "BSD"
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-28 22:32:38 +0000