diff options
Diffstat (limited to 'roms/u-boot/board/freescale/m5253evbe')
| -rw-r--r-- | roms/u-boot/board/freescale/m5253evbe/Makefile | 8 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/m5253evbe/README | 103 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/m5253evbe/config.mk | 9 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/m5253evbe/m5253evbe.c | 125 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/m5253evbe/u-boot.lds | 85 |
5 files changed, 330 insertions, 0 deletions
diff --git a/roms/u-boot/board/freescale/m5253evbe/Makefile b/roms/u-boot/board/freescale/m5253evbe/Makefile new file mode 100644 index 00000000..8c55075c --- /dev/null +++ b/roms/u-boot/board/freescale/m5253evbe/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = m5253evbe.o diff --git a/roms/u-boot/board/freescale/m5253evbe/README b/roms/u-boot/board/freescale/m5253evbe/README new file mode 100644 index 00000000..f51609f3 --- /dev/null +++ b/roms/u-boot/board/freescale/m5253evbe/README @@ -0,0 +1,103 @@ +Freescale Amadeus Plus M5253EVBE board +====================================== + +Hayden Fraser(Hayden.Fraser@freescale.com) +Created 06/05/2007 +=========================================== + + +1. SWITCH SETTINGS +================== +1.1 N/A + + +2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL +=========================================== +2.1. For the initial bringup, we adopted a consistent memory scheme between u-boot and + linux kernel, you can customize it based on your system requirements: + SDR: 0x00000000-0x00ffffff + SRAM0: 0x20010000-0x20017fff + SRAM1: 0x20000000-0x2000ffff + MBAR1: 0x10000000-0x4fffffff + MBAR2: 0x80000000-0xCfffffff + Flash: 0xffe00000-0xffffffff + +3. DEFINITIONS AND COMPILATION +============================== +3.1 Explanation on NEW definitions in include/configs/M5253EVBE.h + CONFIG_MCF52x2 Processor family + CONFIG_MCF5253 MCF5253 specific + CONFIG_M5253EVBE Amadeus Plus board specific + CONFIG_SYS_CLK Define Amadeus Plus CPU Clock + CONFIG_SYS_MBAR MBAR base address + CONFIG_SYS_MBAR2 MBAR2 base address + +3.2 Compilation + export CROSS_COMPILE=/usr/local/freescale-coldfire-4.1-elf/bin/m68k-elf- + cd u-boot-1-2-x + make distclean + make M5253EVBE_config + make + + +4. SCREEN DUMP +============== +4.1 U-Boot 1.2.0 (Jun 18 2007 - 18:20:00) + +CPU: Freescale Coldfire MCF5253 at 62 MHz +Board: Freescale MCF5253 EVBE +DRAM: 16 MB +FLASH: 2 MB +In: serial +Out: serial +Err: serial +=> flinfo + +Bank # 1: CFI conformant FLASH (16 x 16) Size: 2 MB in 35 Sectors + AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x49 + Erase timeout: 16384 ms, write timeout: 1 ms + + Sector Start Addresses: + FFE00000 RO FFE04000 RO FFE06000 RO FFE08000 RO FFE10000 RO + FFE20000 FFE30000 FFE40000 FFE50000 FFE60000 + FFE70000 FFE80000 FFE90000 FFEA0000 FFEB0000 + FFEC0000 FFED0000 FFEE0000 FFEF0000 FFF00000 + FFF10000 FFF20000 FFF30000 FFF40000 FFF50000 + FFF60000 FFF70000 FFF80000 FFF90000 FFFA0000 + FFFB0000 FFFC0000 FFFD0000 FFFE0000 FFFF0000 + +=> bdinfo +boot_params = 0x00F62F90 +memstart = 0x00000000 +memsize = 0x01000000 +flashstart = 0xFFE00000 +flashsize = 0x00200000 +flashoffset = 0x00000000 +baudrate = 19200 bps + +=> printenv +bootdelay=5 +baudrate=19200 +stdin=serial +stdout=serial +stderr=serial + +Environment size: 134/8188 bytes +=> saveenv +Saving Environment to Flash... +Un-Protected 1 sectors +Erasing Flash... +. done +Erased 1 sectors +Writing to Flash... done +Protected 1 sectors +=> + +5. COMPILER +----------- +To create U-Boot the CodeSourcery's version of the GNU Toolchain for the ColdFire architecture +compiler set (freescale-coldfire-4.1-elf) from www.codesourcery.com was used. +You can download it from:http://www.codesourcery.com/gnu_toolchains/coldfire/download.html + +compiler that you used - for example, codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M +codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M diff --git a/roms/u-boot/board/freescale/m5253evbe/config.mk b/roms/u-boot/board/freescale/m5253evbe/config.mk new file mode 100644 index 00000000..1af25e15 --- /dev/null +++ b/roms/u-boot/board/freescale/m5253evbe/config.mk @@ -0,0 +1,9 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +CONFIG_SYS_TEXT_BASE = 0xffe00000 diff --git a/roms/u-boot/board/freescale/m5253evbe/m5253evbe.c b/roms/u-boot/board/freescale/m5253evbe/m5253evbe.c new file mode 100644 index 00000000..15ff755a --- /dev/null +++ b/roms/u-boot/board/freescale/m5253evbe/m5253evbe.c @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. + * Hayden Fraser (Hayden.Fraser@freescale.com) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/immap.h> +#include <asm/io.h> + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale MCF5253 EVBE\n"); + return 0; +}; + +phys_size_t initdram(int board_type) +{ + /* + * Check to see if the SDRAM has already been initialized + * by a run control tool + */ + if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { + u32 RC, dramsize; + + RC = (CONFIG_SYS_CLK / 1000000) >> 1; + RC = (RC * 15) >> 4; + + /* Initialize DRAM Control Register: DCR */ + mbar_writeShort(MCFSIM_DCR, (0x8400 | RC)); + asm("nop"); + + mbar_writeLong(MCFSIM_DACR0, 0x00002320); + asm("nop"); + + /* Initialize DMR0 */ + dramsize = ((CONFIG_SYS_SDRAM_SIZE << 20) - 1) & 0xFFFC0000; + mbar_writeLong(MCFSIM_DMR0, dramsize | 1); + asm("nop"); + + mbar_writeLong(MCFSIM_DACR0, 0x00002328); + asm("nop"); + + /* Write to this block to initiate precharge */ + *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; + asm("nop"); + + /* Set RE bit in DACR */ + mbar_writeLong(MCFSIM_DACR0, + mbar_readLong(MCFSIM_DACR0) | 0x8000); + asm("nop"); + + /* Wait for at least 8 auto refresh cycles to occur */ + udelay(500); + + /* Finish the configuration by issuing the MRS */ + mbar_writeLong(MCFSIM_DACR0, + mbar_readLong(MCFSIM_DACR0) | 0x0040); + asm("nop"); + + *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5; + } + + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; +} + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} + +#ifdef CONFIG_CMD_IDE +#include <ata.h> +int ide_preinit(void) +{ + return (0); +} + +void ide_set_reset(int idereset) +{ + atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; + long period; + /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ + int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ + {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */ + {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */ + {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */ + {25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */ + }; + + if (idereset) { + /* control reset */ + out_8(&ata->cr, 0); + udelay(100); + } else { + mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); + +#define CALC_TIMING(t) (t + period - 1) / period + period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */ + + /*ata->ton = CALC_TIMING (180); */ + out_8(&ata->t1, CALC_TIMING(piotms[2][0])); + out_8(&ata->t2w, CALC_TIMING(piotms[2][1])); + out_8(&ata->t2r, CALC_TIMING(piotms[2][1])); + out_8(&ata->ta, CALC_TIMING(piotms[2][8])); + out_8(&ata->trd, CALC_TIMING(piotms[2][7])); + out_8(&ata->t4, CALC_TIMING(piotms[2][3])); + out_8(&ata->t9, CALC_TIMING(piotms[2][6])); + + /* IORDY enable */ + out_8(&ata->cr, 0x40); + udelay(2000); + /* IORDY enable */ + setbits_8(&ata->cr, 0x01); + } +} +#endif /* CONFIG_CMD_IDE */ diff --git a/roms/u-boot/board/freescale/m5253evbe/u-boot.lds b/roms/u-boot/board/freescale/m5253evbe/u-boot.lds new file mode 100644 index 00000000..e91b7e1e --- /dev/null +++ b/roms/u-boot/board/freescale/m5253evbe/u-boot.lds @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_ARCH(m68k) + +SECTIONS +{ + .text : + { + arch/m68k/cpu/mcf52x2/start.o (.text*) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o (.text) + + *(.text*) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + KEEP(*(.got)) + __got_end = .; + _GOT2_TABLE_ = .; + KEEP(*(.got2)) + _FIXUP_TABLE_ = .; + KEEP(*(.fixup)) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data*) + *(.sdata*) + } + _edata = .; + PROVIDE (edata = .); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + _sbss = .; + *(.bss*) + *(.sbss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + __bss_end = . ; + PROVIDE (end = .); +} |