aboutsummaryrefslogtreecommitdiffstats
path: root/roms/u-boot/board/cpu86
diff options
context:
space:
mode:
Diffstat (limited to 'roms/u-boot/board/cpu86')
-rw-r--r--roms/u-boot/board/cpu86/Makefile8
-rw-r--r--roms/u-boot/board/cpu86/cpu86.c304
-rw-r--r--roms/u-boot/board/cpu86/cpu86.h27
-rw-r--r--roms/u-boot/board/cpu86/flash.c599
4 files changed, 938 insertions, 0 deletions
diff --git a/roms/u-boot/board/cpu86/Makefile b/roms/u-boot/board/cpu86/Makefile
new file mode 100644
index 00000000..da83afd7
--- /dev/null
+++ b/roms/u-boot/board/cpu86/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = cpu86.o flash.o
diff --git a/roms/u-boot/board/cpu86/cpu86.c b/roms/u-boot/board/cpu86/cpu86.c
new file mode 100644
index 00000000..92929105
--- /dev/null
+++ b/roms/u-boot/board/cpu86/cpu86.c
@@ -0,0 +1,304 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include "cpu86.h"
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
+ /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
+ /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
+ /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
+ /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
+ /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
+ /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */
+ /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */
+ /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */
+ /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */
+ /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
+ /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
+ /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
+ /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
+ /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
+ /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
+ /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
+ /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
+ /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */
+ /* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */
+ /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */
+ /* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */
+ /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
+ /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
+ /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
+ /* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */
+ /* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */
+ /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */
+ /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */
+ /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
+ /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */
+ /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
+ /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
+ /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
+ /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
+ /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
+ /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
+ /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
+ /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
+ /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
+ /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
+ /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
+ /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
+ /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
+ /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
+ /* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */
+ /* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */
+ /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
+ /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */
+ /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */
+ /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
+ /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
+ /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
+ /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
+ /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
+ /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
+ /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */
+ /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
+ /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
+ /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
+ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */
+ /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */
+ /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
+ /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */
+ /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */
+ /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
+ /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
+#if defined(CONFIG_SYS_I2C_SOFT)
+ /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
+ /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+ /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
+#else /* normal I/O port pins */
+ /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
+#endif
+#endif
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
+ /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
+ /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */
+ }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+ printf ("Board: CPU86 (Rev %02x)\n", CPU86_REV);
+ return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+ ulong orx, volatile uchar * base)
+{
+ volatile uchar c = 0xff;
+ volatile uint *sdmr_ptr;
+ volatile uint *orx_ptr;
+ ulong maxsize, size;
+ int i;
+
+ /* We must be able to test a location outsize the maximum legal size
+ * to find out THAT we are outside; but this address still has to be
+ * mapped by the controller. That means, that the initial mapping has
+ * to be (at least) twice as large as the maximum expected size.
+ */
+ maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+ /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
+ * we are configuring CS1 if base != 0
+ */
+ sdmr_ptr = &memctl->memc_psdmr;
+ orx_ptr = &memctl->memc_or2;
+
+ *orx_ptr = orx;
+
+ /*
+ * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+ *
+ * "At system reset, initialization software must set up the
+ * programmable parameters in the memory controller banks registers
+ * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+ * system software should execute the following initialization sequence
+ * for each SDRAM device.
+ *
+ * 1. Issue a PRECHARGE-ALL-BANKS command
+ * 2. Issue eight CBR REFRESH commands
+ * 3. Issue a MODE-SET command to initialize the mode register
+ *
+ * The initial commands are executed by setting P/LSDMR[OP] and
+ * accessing the SDRAM with a single-byte transaction."
+ *
+ * The appropriate BRx/ORx registers have already been set when we
+ * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+ */
+
+ *sdmr_ptr = sdmr | PSDMR_OP_PREA;
+ *base = c;
+
+ *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+ for (i = 0; i < 8; i++)
+ *base = c;
+
+ *sdmr_ptr = sdmr | PSDMR_OP_MRW;
+ *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
+
+ *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+ *base = c;
+
+ size = get_ram_size((long *)base, maxsize);
+
+ *orx_ptr = orx | ~(size - 1);
+
+ return (size);
+}
+
+phys_size_t initdram (int board_type)
+{
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+ volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifndef CONFIG_SYS_RAMBOOT
+ ulong size8, size9;
+#endif
+ long psize;
+
+ psize = 32 * 1024 * 1024;
+
+ memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+ memctl->memc_psrt = CONFIG_SYS_PSRT;
+
+#ifndef CONFIG_SYS_RAMBOOT
+ /* 60x SDRAM setup:
+ */
+ size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+ (uchar *) CONFIG_SYS_SDRAM_BASE);
+ size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
+ (uchar *) CONFIG_SYS_SDRAM_BASE);
+
+ if (size8 < size9) {
+ psize = size9;
+ printf ("(60x:9COL) ");
+ } else {
+ psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+ (uchar *) CONFIG_SYS_SDRAM_BASE);
+ printf ("(60x:8COL) ");
+ }
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+ icache_enable ();
+
+ return (psize);
+}
+
+#if defined(CONFIG_CMD_DOC)
+void doc_init (void)
+{
+ doc_probe (CONFIG_SYS_DOC_BASE);
+}
+#endif
diff --git a/roms/u-boot/board/cpu86/cpu86.h b/roms/u-boot/board/cpu86/cpu86.h
new file mode 100644
index 00000000..ca0c39f6
--- /dev/null
+++ b/roms/u-boot/board/cpu86/cpu86.h
@@ -0,0 +1,27 @@
+#ifndef __BOARD_CPU86__
+#define __BOARD_CPU86__
+
+#include <config.h>
+
+#define REG8(x) (*(volatile unsigned char *)(x))
+
+/* CPU86 register definitions */
+#define CPU86_VME_EAC REG8(CONFIG_SYS_BCRS_BASE + 0x00)
+#define CPU86_VME_SAC REG8(CONFIG_SYS_BCRS_BASE + 0x01)
+#define CPU86_VME_MAC REG8(CONFIG_SYS_BCRS_BASE + 0x02)
+#define CPU86_BCR REG8(CONFIG_SYS_BCRS_BASE + 0x03)
+#define CPU86_BSR REG8(CONFIG_SYS_BCRS_BASE + 0x04)
+#define CPU86_WDOG_RPORT REG8(CONFIG_SYS_BCRS_BASE + 0x05)
+#define CPU86_MBOX_IRQ REG8(CONFIG_SYS_BCRS_BASE + 0x04)
+#define CPU86_REV REG8(CONFIG_SYS_BCRS_BASE + 0x07)
+#define CPU86_VME_IRQMASK REG8(CONFIG_SYS_BCRS_BASE + 0x80)
+#define CPU86_VME_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x81)
+#define CPU86_LOCAL_IRQMASK REG8(CONFIG_SYS_BCRS_BASE + 0x82)
+#define CPU86_LOCAL_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x83)
+#define CPU86_PMCL_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x84)
+
+/* Board Control Register bits */
+#define CPU86_BCR_FWPT 0x01
+#define CPU86_BCR_FWRE 0x02
+
+#endif /* __BOARD_CPU86__ */
diff --git a/roms/u-boot/board/cpu86/flash.c b/roms/u-boot/board/cpu86/flash.c
new file mode 100644
index 00000000..b99a9a08
--- /dev/null
+++ b/roms/u-boot/board/cpu86/flash.c
@@ -0,0 +1,599 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for Intel devices
+ *
+ *--------------------------------------------------------------------
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "cpu86.h"
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_int_get_size (volatile unsigned long *baseaddr,
+ flash_info_t * info)
+{
+ short i;
+ unsigned long flashtest_h, flashtest_l;
+
+ info->sector_count = info->size = 0;
+ info->flash_id = FLASH_UNKNOWN;
+
+ /* Write identify command sequence and test FLASH answer
+ */
+ baseaddr[0] = 0x00900090;
+ baseaddr[1] = 0x00900090;
+
+ flashtest_h = baseaddr[0]; /* manufacturer ID */
+ flashtest_l = baseaddr[1];
+
+ if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT)
+ return (0); /* no or unknown flash */
+
+ flashtest_h = baseaddr[2]; /* device ID */
+ flashtest_l = baseaddr[3];
+
+ if (flashtest_h != flashtest_l)
+ return (0);
+
+ switch (flashtest_h) {
+ case INTEL_ID_28F160C3B:
+ info->flash_id = FLASH_28F160C3B;
+ info->sector_count = 39;
+ info->size = 0x00800000; /* 4 * 2 MB = 8 MB */
+ break;
+ case INTEL_ID_28F160F3B:
+ info->flash_id = FLASH_28F160F3B;
+ info->sector_count = 39;
+ info->size = 0x00800000; /* 4 * 2 MB = 8 MB */
+ break;
+ default:
+ return (0); /* no or unknown flash */
+ }
+
+ info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */
+
+ if (info->flash_id & FLASH_BTYPE) {
+ volatile unsigned long *tmp = baseaddr;
+
+ /* set up sector start adress table (bottom sector type)
+ * AND unlock the sectors (if our chip is 160C3)
+ */
+ for (i = 0; i < info->sector_count; i++) {
+ if ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) {
+ tmp[0] = 0x00600060;
+ tmp[1] = 0x00600060;
+ tmp[0] = 0x00D000D0;
+ tmp[1] = 0x00D000D0;
+ }
+ info->start[i] = (uint) tmp;
+ tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith */
+ }
+ }
+
+ memset (info->protect, 0, info->sector_count);
+
+ baseaddr[0] = 0x00FF00FF;
+ baseaddr[1] = 0x00FF00FF;
+
+ return (info->size);
+}
+
+static ulong flash_amd_get_size (vu_char *addr, flash_info_t *info)
+{
+ short i;
+ uchar vendor, devid;
+ ulong base = (ulong)addr;
+
+ /* Write auto select command: read Manufacturer ID */
+ addr[0x0555] = 0xAA;
+ addr[0x02AA] = 0x55;
+ addr[0x0555] = 0x90;
+
+ udelay(1000);
+
+ vendor = addr[0];
+ devid = addr[1] & 0xff;
+
+ /* only support AMD */
+ if (vendor != 0x01) {
+ return 0;
+ }
+
+ vendor &= 0xf;
+ devid &= 0xff;
+
+ if (devid == AMD_ID_F040B) {
+ info->flash_id = vendor << 16 | devid;
+ info->sector_count = 8;
+ info->size = info->sector_count * 0x10000;
+ }
+ else if (devid == AMD_ID_F080B) {
+ info->flash_id = vendor << 16 | devid;
+ info->sector_count = 16;
+ info->size = 4 * info->sector_count * 0x10000;
+ }
+ else if (devid == AMD_ID_F016D) {
+ info->flash_id = vendor << 16 | devid;
+ info->sector_count = 32;
+ info->size = 4 * info->sector_count * 0x10000;
+ }
+ else {
+ printf ("## Unknown Flash Type: %02x\n", devid);
+ return 0;
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* sector base address */
+ info->start[i] = base + i * (info->size / info->sector_count);
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr = (volatile unsigned char *)(info->start[i]);
+ info->protect[i] = addr[2] & 1;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ addr = (vu_char *)info->start[0];
+ addr[0] = 0xF0; /* reset bank */
+ }
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+ unsigned long size_b0 = 0;
+ unsigned long size_b1 = 0;
+ int i;
+
+ /* Init: no FLASHes known
+ */
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Disable flash protection */
+ CPU86_BCR |= (CPU86_BCR_FWPT | CPU86_BCR_FWRE);
+
+ /* Static FLASH Bank configuration here (only one bank) */
+
+ size_b0 = flash_int_get_size ((ulong *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+ size_b1 = flash_amd_get_size ((uchar *) CONFIG_SYS_BOOTROM_BASE, &flash_info[1]);
+
+ if (size_b0 > 0 || size_b1 > 0) {
+
+ printf("(");
+
+ if (size_b0 > 0) {
+ puts ("Bank#1 - ");
+ print_size (size_b0, (size_b1 > 0) ? ", " : ") ");
+ }
+
+ if (size_b1 > 0) {
+ puts ("Bank#2 - ");
+ print_size (size_b1, ") ");
+ }
+ }
+ else {
+ printf ("## No FLASH found.\n");
+ return 0;
+ }
+ /* protect monitor and environment sectors
+ */
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_BOOTROM_BASE
+ if (size_b1) {
+ /* If U-Boot is booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH_BASE
+ * but we shouldn't protect it.
+ */
+
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]
+ );
+ }
+#else
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
+ );
+#endif
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+# ifndef CONFIG_ENV_SIZE
+# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+# endif
+# if CONFIG_ENV_ADDR >= CONFIG_SYS_BOOTROM_BASE
+ if (size_b1) {
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]);
+ }
+# else
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+# endif
+#endif
+
+ return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch ((info->flash_id >> 16) & 0xff) {
+ case 0x89:
+ printf ("INTEL ");
+ break;
+ case 0x1:
+ printf ("AMD ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F160C3B:
+ printf ("28F160C3B (16 Mbit, bottom sector)\n");
+ break;
+ case FLASH_28F160F3B:
+ printf ("28F160F3B (16 Mbit, bottom sector)\n");
+ break;
+ case AMD_ID_F040B:
+ printf ("AM29F040B (4 Mbit)\n");
+ break;
+ default:
+ printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ if (info->size < 0x100000)
+ printf (" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+ else
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+ vu_char *addr = (vu_char *)(info->start[0]);
+ int flag, prot, sect, l_sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect])
+ prot++;
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ /* Check the type of erased flash
+ */
+ if (info->flash_id >> 16 == 0x1) {
+ /* Erase AMD flash
+ */
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr[0x0555] = 0xAA;
+ addr[0x02AA] = 0x55;
+ addr[0x0555] = 0x80;
+ addr[0x0555] = 0xAA;
+ addr[0x02AA] = 0x55;
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr = (vu_char *)(info->start[sect]);
+ addr[0] = 0x30;
+ l_sect = sect;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto AMD_DONE;
+
+ start = get_timer (0);
+ last = start;
+ addr = (vu_char *)(info->start[l_sect]);
+ while ((addr[0] & 0x80) != 0x80) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ serial_putc ('.');
+ last = now;
+ }
+ }
+
+AMD_DONE:
+ /* reset to read mode */
+ addr = (volatile unsigned char *)info->start[0];
+ addr[0] = 0xF0; /* reset bank */
+
+ } else {
+ /* Erase Intel flash
+ */
+
+ /* Start erase on unprotected sectors
+ */
+ for (sect = s_first; sect <= s_last; sect++) {
+ volatile ulong *addr =
+ (volatile unsigned long *) info->start[sect];
+
+ start = get_timer (0);
+ last = start;
+ if (info->protect[sect] == 0) {
+ /* Disable interrupts which might cause a timeout here
+ */
+ flag = disable_interrupts ();
+
+ /* Erase the block
+ */
+ addr[0] = 0x00200020;
+ addr[1] = 0x00200020;
+ addr[0] = 0x00D000D0;
+ addr[1] = 0x00D000D0;
+
+ /* re-enable interrupts if necessary
+ */
+ if (flag)
+ enable_interrupts ();
+
+ /* wait at least 80us - let's wait 1 ms
+ */
+ udelay (1000);
+
+ last = start;
+ while ((addr[0] & 0x00800080) != 0x00800080 ||
+ (addr[1] & 0x00800080) != 0x00800080) {
+ if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf ("Timeout (erase suspended!)\n");
+ /* Suspend erase
+ */
+ addr[0] = 0x00B000B0;
+ addr[1] = 0x00B000B0;
+ goto DONE;
+ }
+ /* show that we're waiting
+ */
+ if ((now - last) > 1000) { /* every second */
+ serial_putc ('.');
+ last = now;
+ }
+ }
+ if (addr[0] & 0x00220022 || addr[1] & 0x00220022) {
+ printf ("*** ERROR: erase failed!\n");
+ goto DONE;
+ }
+ }
+ /* Clear status register and reset to read mode
+ */
+ addr[0] = 0x00500050;
+ addr[1] = 0x00500050;
+ addr[0] = 0x00FF00FF;
+ addr[1] = 0x00FF00FF;
+ }
+ }
+
+ printf (" done\n");
+
+DONE:
+ return 0;
+}
+
+static int write_word (flash_info_t *, volatile unsigned long *, ulong);
+static int write_byte (flash_info_t *info, ulong dest, uchar data);
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong v;
+ int i, l, rc, cc = cnt, res = 0;
+
+ if (info->flash_id >> 16 == 0x1) {
+
+ /* Write to AMD 8-bit flash
+ */
+ while (cnt > 0) {
+ if ((rc = write_byte(info, addr, *src)) != 0) {
+ return (rc);
+ }
+ addr++;
+ src++;
+ cnt--;
+ }
+
+ return (0);
+ } else {
+
+ /* Write to Intel 64-bit flash
+ */
+ for (v=0; cc > 0; addr += 4, cc -= 4 - l) {
+ l = (addr & 3);
+ addr &= ~3;
+
+ for (i = 0; i < 4; i++) {
+ v = (v << 8) + (i < l || i - l >= cc ?
+ *((unsigned char *) addr + i) : *src++);
+ }
+
+ if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0)
+ break;
+ }
+ }
+
+ return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, volatile unsigned long *addr,
+ ulong data)
+{
+ int flag, res = 0;
+ ulong start;
+
+ /* Check if Flash is (sufficiently) erased
+ */
+ if ((*addr & data) != data)
+ return (2);
+
+ /* Disable interrupts which might cause a timeout here
+ */
+ flag = disable_interrupts ();
+
+ *addr = 0x00400040;
+ *addr = data;
+
+ /* re-enable interrupts if necessary
+ */
+ if (flag)
+ enable_interrupts ();
+
+ start = get_timer (0);
+ while ((*addr & 0x00800080) != 0x00800080) {
+ if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ /* Suspend program
+ */
+ *addr = 0x00B000B0;
+ res = 1;
+ goto OUT;
+ }
+ }
+
+ if (*addr & 0x00220022) {
+ printf ("*** ERROR: program failed!\n");
+ res = 1;
+ }
+
+OUT:
+ /* Clear status register and reset to read mode
+ */
+ *addr = 0x00500050;
+ *addr = 0x00FF00FF;
+
+ return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a byte to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte (flash_info_t *info, ulong dest, uchar data)
+{
+ vu_char *addr = (vu_char *)(info->start[0]);
+ ulong start;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_char *)dest) & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr[0x0555] = 0xAA;
+ addr[0x02AA] = 0x55;
+ addr[0x0555] = 0xA0;
+
+ *((vu_char *)dest) = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 18:39:17 +0000