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author | fishsoupisgood <github@madingley.org> | 2019-04-29 01:17:54 +0100 |
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committer | fishsoupisgood <github@madingley.org> | 2019-05-27 03:43:43 +0100 |
commit | 3f2546b2ef55b661fd8dd69682b38992225e86f6 (patch) | |
tree | 65ca85f13617aee1dce474596800950f266a456c /target-openrisc/interrupt_helper.c | |
download | qemu-3f2546b2ef55b661fd8dd69682b38992225e86f6.tar.gz qemu-3f2546b2ef55b661fd8dd69682b38992225e86f6.tar.bz2 qemu-3f2546b2ef55b661fd8dd69682b38992225e86f6.zip |
Diffstat (limited to 'target-openrisc/interrupt_helper.c')
-rw-r--r-- | target-openrisc/interrupt_helper.c | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/target-openrisc/interrupt_helper.c b/target-openrisc/interrupt_helper.c new file mode 100644 index 00000000..55a780c7 --- /dev/null +++ b/target-openrisc/interrupt_helper.c @@ -0,0 +1,58 @@ +/* + * OpenRISC interrupt helper routines + * + * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> + * Feng Gao <gf91597@gmail.com> + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ + +#include "cpu.h" +#include "exec/helper-proto.h" + +void HELPER(rfe)(CPUOpenRISCState *env) +{ + OpenRISCCPU *cpu = openrisc_env_get_cpu(env); + CPUState *cs = CPU(cpu); +#ifndef CONFIG_USER_ONLY + int need_flush_tlb = (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^ + (cpu->env.esr & (SR_SM | SR_IME | SR_DME)); +#endif + cpu->env.pc = cpu->env.epcr; + cpu->env.npc = cpu->env.epcr; + cpu->env.sr = cpu->env.esr; + +#ifndef CONFIG_USER_ONLY + if (cpu->env.sr & SR_DME) { + cpu->env.tlb->cpu_openrisc_map_address_data = + &cpu_openrisc_get_phys_data; + } else { + cpu->env.tlb->cpu_openrisc_map_address_data = + &cpu_openrisc_get_phys_nommu; + } + + if (cpu->env.sr & SR_IME) { + cpu->env.tlb->cpu_openrisc_map_address_code = + &cpu_openrisc_get_phys_code; + } else { + cpu->env.tlb->cpu_openrisc_map_address_code = + &cpu_openrisc_get_phys_nommu; + } + + if (need_flush_tlb) { + tlb_flush(cs, 1); + } +#endif + cs->interrupt_request |= CPU_INTERRUPT_EXITTB; +} |