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authorfishsoupisgood <github@madingley.org>2019-04-29 01:17:54 +0100
committerfishsoupisgood <github@madingley.org>2019-05-27 03:43:43 +0100
commit3f2546b2ef55b661fd8dd69682b38992225e86f6 (patch)
tree65ca85f13617aee1dce474596800950f266a456c /roms/u-boot/arch/nios2/include/asm/dma-mapping.h
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Initial import of qemu-2.4.1HEADmaster
Diffstat (limited to 'roms/u-boot/arch/nios2/include/asm/dma-mapping.h')
-rw-r--r--roms/u-boot/arch/nios2/include/asm/dma-mapping.h23
1 files changed, 23 insertions, 0 deletions
diff --git a/roms/u-boot/arch/nios2/include/asm/dma-mapping.h b/roms/u-boot/arch/nios2/include/asm/dma-mapping.h
new file mode 100644
index 00000000..1350e3b9
--- /dev/null
+++ b/roms/u-boot/arch/nios2/include/asm/dma-mapping.h
@@ -0,0 +1,23 @@
+#ifndef __ASM_NIOS2_DMA_MAPPING_H
+#define __ASM_NIOS2_DMA_MAPPING_H
+
+/* dma_alloc_coherent() return cache-line aligned allocation which is mapped
+ * to uncached io region.
+ *
+ * IO_REGION_BASE should be defined in board config header file
+ * 0x80000000 for nommu, 0xe0000000 for mmu
+ */
+
+static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
+{
+ void *addr = malloc(len + CONFIG_SYS_DCACHELINE_SIZE);
+ if (!addr)
+ return 0;
+ flush_dcache((unsigned long)addr, len + CONFIG_SYS_DCACHELINE_SIZE);
+ *handle = ((unsigned long)addr +
+ (CONFIG_SYS_DCACHELINE_SIZE - 1)) &
+ ~(CONFIG_SYS_DCACHELINE_SIZE - 1) & ~(IO_REGION_BASE);
+ return (void *)(*handle | IO_REGION_BASE);
+}
+
+#endif /* __ASM_NIOS2_DMA_MAPPING_H */