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author | fishsoupisgood <github@madingley.org> | 2019-05-28 10:47:31 +0100 |
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committer | fishsoupisgood <github@madingley.org> | 2019-05-28 10:47:31 +0100 |
commit | ee80143bdd65f7ed6234cac60881c2b42b854814 (patch) | |
tree | af20e6600e5f8d73a6fbf74b20c7e191a0108c7c /master/timex-instructions.patch | |
parent | 3e79d2f5d768fa7ac63fdad196a5e32fbaeffcaf (diff) | |
download | asl-pq-ee80143bdd65f7ed6234cac60881c2b42b854814.tar.gz asl-pq-ee80143bdd65f7ed6234cac60881c2b42b854814.tar.bz2 asl-pq-ee80143bdd65f7ed6234cac60881c2b42b854814.zip |
add undocumented BRSKIP2 instruction
Diffstat (limited to 'master/timex-instructions.patch')
-rw-r--r-- | master/timex-instructions.patch | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/master/timex-instructions.patch b/master/timex-instructions.patch new file mode 100644 index 0000000..c9633cf --- /dev/null +++ b/master/timex-instructions.patch @@ -0,0 +1,21 @@ +diff --git a/code6805.c b/code6805.c +index 0a087af..b89161e 100644 +--- a/code6805.c ++++ b/code6805.c +@@ -47,7 +47,7 @@ typedef struct + Word Mask; + } RMWOrder; + +-#define FixedOrderCnt 52 ++#define FixedOrderCnt 53 + #define RelOrderCnt 23 + #define ALUOrderCnt 19 + #define RMWOrderCnt 12 +@@ -150,6 +150,7 @@ BEGIN + AddFixed("STOP",CPU6805,0x8e); AddFixed("TAP" ,CPU6808,0x84); + AddFixed("TPA" ,CPU6808,0x85); AddFixed("TSX" ,CPU6808,0x95); + AddFixed("TXS" ,CPU6808,0x94); AddFixed("WAIT",CPU6805,0x8f); ++ AddFixed("BRSKIP2" ,CPU6805,0xc5); + + RelOrders=(BaseOrder *) malloc(sizeof(BaseOrder)*RelOrderCnt); InstrZ=0; + AddRel("BRA" ,CPU6805,0x20); AddRel("BRN" ,CPU6805,0x21); |