blob: f4efee1bbfb901b505f68a9e30710bb710500d87 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
|
#define PHY PHY1
#define TXEN GPIO11
#define TXEN_PORT GPIOG
#define TXD0 GPIO13
#define TXD0_PORT GPIOG
#define TXD1 GPIO14
#define TXD1_PORT GPIOG
#define RXD0 GPIO4
#define RXD0_PORT GPIOC
#define RXD1 GPIO5
#define RXD1_PORT GPIOC
#define CRS_DV GPIO7
#define CRS_DV_PORT GPIOA
#define MDIO GPIO2
#define MDIO_PORT GPIOA
#define MDC GPIO1
#define MDC_PORT GPIOC
#define REF_CLK GPIO1
#define REF_CLK_PORT GPIOA
#define DESC_SZ ETH_DES_EXT_SIZE
#define FRAME_SZ 1516
#define TX_BUFS 4
#define RX_BUFS 4
#define ETH_BUF_LEN ((TX_BUFS+ RX_BUFS) * (DESC_SZ+FRAME_SZ))
|
