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* working, with hybrid FLL/PLL, new refclk input and support for max7219 displa...root2021-03-021-22/+46
* worksroot2021-02-261-2/+12
* timroot2021-02-251-3/+23
* sysclk back to 168MHz, 10Mhz -> TIM2old-masterfishsoupisgood2019-05-081-0/+4
* cut #1fishsoupisgood2019-05-041-11/+25
* switch to stlink, blinkyroot2019-02-221-1/+4
* use OCXO, and auto fail-over between different clock sourcesfishsoupisgood2019-02-201-18/+4
* Workingroot2019-02-191-0/+3
* everything working, even with fucked phyroot2019-02-191-1/+4
* working ethernetroot2019-02-191-6/+32
* happy dcf77 better pll, and stamps for long term stabilityroot2018-04-171-3/+23
* working decodingroot2018-04-081-0/+64