Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | working, with hybrid FLL/PLL, new refclk input and support for max7219 displa... | root | 2021-03-02 | 1 | -22/+46 |
* | works | root | 2021-02-26 | 1 | -2/+12 |
* | tim | root | 2021-02-25 | 1 | -3/+23 |
* | sysclk back to 168MHz, 10Mhz -> TIM2old-master | fishsoupisgood | 2019-05-08 | 1 | -0/+4 |
* | cut #1 | fishsoupisgood | 2019-05-04 | 1 | -11/+25 |
* | switch to stlink, blinky | root | 2019-02-22 | 1 | -1/+4 |
* | use OCXO, and auto fail-over between different clock sources | fishsoupisgood | 2019-02-20 | 1 | -18/+4 |
* | Working | root | 2019-02-19 | 1 | -0/+3 |
* | everything working, even with fucked phy | root | 2019-02-19 | 1 | -1/+4 |
* | working ethernet | root | 2019-02-19 | 1 | -6/+32 |
* | happy dcf77 better pll, and stamps for long term stability | root | 2018-04-17 | 1 | -3/+23 |
* | working decoding | root | 2018-04-08 | 1 | -0/+64 |