| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | working, with hybrid FLL/PLL, new refclk input and support for max7219 displa... | root | 2021-03-02 | 1 | -9/+12 |
| * | tim | root | 2021-02-25 | 1 | -3/+3 |
| * | sysclk back to 168MHz, 10Mhz -> TIM2old-master | fishsoupisgood | 2019-05-08 | 1 | -1/+1 |
| * | cut #1 | fishsoupisgood | 2019-05-04 | 1 | -39/+57 |
| * | switch to stlink, blinky | root | 2019-02-22 | 1 | -1/+1 |
| * | use OCXO, and auto fail-over between different clock sources | fishsoupisgood | 2019-02-20 | 1 | -3/+19 |
| * | fix offsets | root | 2019-02-19 | 1 | -3/+2 |
| * | Working | root | 2019-02-19 | 1 | -2/+2 |
| * | everything working, even with fucked phy | root | 2019-02-19 | 1 | -10/+8 |
| * | working ethernet | root | 2019-02-19 | 1 | -1/+3 |
| * | happy dcf77 better pll, and stamps for long term stability | root | 2018-04-17 | 1 | -44/+43 |
| * | working decoding | root | 2018-04-08 | 1 | -0/+226 |
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index : stm32/clock | |
| code for gps/dcf77/msf clock | James |
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