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* working, with hybrid FLL/PLL, new refclk input and support for max7219 displa...root2021-03-021-15/+45
* worksroot2021-02-261-14/+30
* timroot2021-02-251-68/+300
* sysclk back to 168MHz, 10Mhz -> TIM2old-masterfishsoupisgood2019-05-081-12/+21
* cut #1fishsoupisgood2019-05-041-39/+277
* switch to stlink, blinkyroot2019-02-221-1/+1
* use OCXO, and auto fail-over between different clock sourcesfishsoupisgood2019-02-201-11/+20
* fix offsetsroot2019-02-191-14/+13
* Workingroot2019-02-191-16/+21
* everything working, even with fucked phyroot2019-02-191-41/+64
* working ethernetroot2019-02-191-0/+839