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* working, with hybrid FLL/PLL, new refclk input and support for max7219 displa...root2021-03-021-7/+10
* worksroot2021-02-261-1/+1
* timroot2021-02-251-4/+4
* sysclk back to 168MHz, 10Mhz -> TIM2old-masterfishsoupisgood2019-05-081-1/+1
* cut #1fishsoupisgood2019-05-041-32/+57
* switch to stlink, blinkyroot2019-02-221-1/+1
* use OCXO, and auto fail-over between different clock sourcesfishsoupisgood2019-02-201-2/+7
* fix offsetsroot2019-02-191-7/+12
* everything working, even with fucked phyroot2019-02-191-4/+2
* working ethernetroot2019-02-191-0/+186