summaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
* sysclk back to 168MHz, 10Mhz -> TIM2old-masterfishsoupisgood2019-05-0813-86/+300
* switch to 10MHz system clockfishsoupisgood2019-05-042-61/+148
* cut #1fishsoupisgood2019-05-0428-229/+2277
* fishJames2019-02-251-1/+1
* switch to stlink, blinkyroot2019-02-2215-82/+194
* add edge magicfishsoupisgood2019-02-213-7/+17
* use OCXO, and auto fail-over between different clock sourcesfishsoupisgood2019-02-2011-48/+109
* fix offsetsroot2019-02-196-45/+54
* Workingroot2019-02-1912-436/+650
* everything working, even with fucked phyroot2019-02-1913-389/+509
* working ethernetroot2019-02-1925-174/+1712
* remember old stethroot2019-02-191-12/+73
* happy dcf77 better pll, and stamps for long term stabilityroot2018-04-179-89/+148
* working decodingroot2018-04-0845-0/+3088