diff options
Diffstat (limited to 'app/main.c')
| -rw-r--r-- | app/main.c | 176 |
1 files changed, 20 insertions, 156 deletions
@@ -84,160 +84,25 @@ static void cmd_dispatch (void) } -#if 0 -static void pd_port (uint32_t p) -{ - unsigned c; - - for (c = 0; c < 32; ++c) { - - if ((p == GPIOA) && ((c == 13) || (c == 14))) continue; - - gpio_mode_setup (p, GPIO_MODE_INPUT, GPIO_PUPD_NONE, 1UL << c); - } -} - - -static void pd_clear (uint32_t g, uint32_t b) -{ - gpio_mode_setup (g, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, b); - gpio_set_output_options (g, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, b); - gpio_clear (g, b); -} - - -static void pd_set (uint32_t g, uint32_t b) -{ - gpio_mode_setup (g, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, b); - gpio_set_output_options (g, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, b); - gpio_set (g, b); -} - - -static void pd (void) -{ - pd_port (GPIOA); - pd_port (GPIOB); - pd_port (GPIOC); - pd_port (GPIOD); - pd_port (GPIOE); - pd_port (GPIOF); - pd_port (GPIOG); - - - pd_set (GPIOB, GPIO10); - - pd_set (GPIOG, GPIO4); - pd_set (GPIOD, GPIO10); - - pd_set (GPIOD, GPIO1); - pd_set (GPIOB, GPIO13); - - pd_set (GPIOE, GPIO3); - pd_set (GPIOE, GPIO4); - - - rcc_periph_clock_disable (RCC_ETHMACPTP); - rcc_periph_clock_disable (RCC_ETHMACRX); - rcc_periph_clock_disable (RCC_ETHMACTX); - rcc_periph_clock_disable (RCC_ETHMAC); - rcc_periph_clock_disable (RCC_USART2); - rcc_periph_clock_disable (RCC_USART1); - rcc_periph_clock_disable (RCC_GPIOG); - rcc_periph_clock_disable (RCC_GPIOF); - rcc_periph_clock_disable (RCC_GPIOE); - rcc_periph_clock_disable (RCC_GPIOD); - rcc_periph_clock_disable (RCC_GPIOC); - rcc_periph_clock_disable (RCC_GPIOB); - rcc_periph_clock_disable (RCC_GPIOA); - rcc_periph_clock_disable (RCC_SYSCFG); - - - - for (;;); -} -#endif - - -static const clock_scale_t hse_10mhz_3v3_168 = { - /* 168MHz */ +const struct rcc_clock_scale hse_10mhz_3v3_168 = { .pllm = 10, .plln = 336, .pllp = 2, .pllq = 7, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPRE_DIV4, + .ppre2 = RCC_CFGR_PPRE_DIV2, + .voltage_scale = PWR_SCALE1, + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_5WS, + .ahb_frequency = 168000000, .apb1_frequency = 42000000, .apb2_frequency = 84000000, }; -#if 0 -static const clock_scale_t hse_10mhz_3v3_120 = { - /* 120 */ - .pllm = 10, - .plln = 240, - .pllp = 2, - .pllq = 5, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .power_save = 1, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | - FLASH_ACR_LATENCY_3WS, - .apb1_frequency = 30000000, - .apb2_frequency = 60000000, -}; - -static const clock_scale_t hse_10mhz_3v3_84 = { - .pllm = 10, - .plln = 336, - .pllp = 4, - .pllq = 7, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_2, - .ppre2 = RCC_CFGR_PPRE_DIV_NONE, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | - FLASH_ACR_LATENCY_2WS, - .apb1_frequency = 42000000, - .apb2_frequency = 84000000, -}; - - -static const clock_scale_t hse_10mhz_3v3_48 = { - .pllm = 10, - .plln = 96, - .pllp = 2, - .pllq = 2, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .power_save = 1, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | - FLASH_ACR_LATENCY_3WS, - .apb1_frequency = 12000000, - .apb2_frequency = 24000000, -}; - -static const clock_scale_t hse_10mhz_3v3_10 = { - /* 10 */ - .pllm = 10, - .plln = 336, - .pllp = 2, - .pllq = 7, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_NONE, - .ppre2 = RCC_CFGR_PPRE_DIV_NONE, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_0WS, - // .ahb_frequency = 10000000, - .apb1_frequency = 10000000, - .apb2_frequency = 10000000, -}; - -#endif static void ptp_clock_start (void) { @@ -268,23 +133,23 @@ static void clock_setup (void) */ /*Get us up and running on the 16MHz RC clock */ - rcc_osc_on (HSI); - rcc_wait_for_osc_ready (HSI); + rcc_osc_on (RCC_HSI); + rcc_wait_for_osc_ready (RCC_HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source (RCC_CFGR_SW_HSI); /* confiure HSE as input not oscillator */ - rcc_osc_bypass_enable (HSE); - rcc_osc_on (HSE); + rcc_osc_bypass_enable (RCC_HSE); + rcc_osc_on (RCC_HSE); while ((RCC_CR & RCC_CR_HSERDY) == 0) { if (fail++ == 4000000) { /*No external clock, try seeing if we have a crystal */ - rcc_osc_off (HSE); - rcc_osc_bypass_disable (HSE); - rcc_osc_on (HSE); + rcc_osc_off (RCC_HSE); + rcc_osc_bypass_disable (RCC_HSE); + rcc_osc_on (RCC_HSE); } } @@ -299,8 +164,7 @@ static void clock_setup (void) RCC_CFGR &= ~ (RCC_CFGR_MCOPRE_DIV_5 << RCC_CFGR_MCO1PRE_SHIFT); RCC_CFGR |= RCC_CFGR_MCOPRE_DIV_NONE << RCC_CFGR_MCO1PRE_SHIFT; - rcc_clock_setup_hse_3v3 (&hse_10mhz_3v3_168); - /* rcc_clock_setup_hse_3v3_no_pll (&hse_10mhz_3v3_10); */ + rcc_clock_setup_pll (&hse_10mhz_3v3_168); } @@ -340,7 +204,7 @@ static void timer_setup (void) */ - timer_reset (TIM1); + rcc_periph_reset_pulse (RST_TIM1); timer_set_mode (TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); /* meh */ timer_slave_set_filter (TIM1, TIM_SMCR_ETF_OFF); /* No filter */ timer_slave_set_prescaler (TIM1, TIM_SMCR_ETPS_OFF); /* no prescaler */ @@ -349,7 +213,7 @@ static void timer_setup (void) timer_set_master_mode (TIM1, TIM_CR2_MMS_RESET); /* output reset on TRGO */ timer_enable_counter (TIM1); /* go */ - timer_reset (TIM2); + rcc_periph_reset_pulse (RST_TIM2); timer_set_mode (TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); /* count up with clock*/ timer_slave_set_filter (TIM2, TIM_SMCR_ETF_OFF); /*no filter*/ timer_slave_set_prescaler (TIM2, TIM_SMCR_ETPS_OFF); /*no prescaler */ @@ -367,7 +231,7 @@ static void timer_setup (void) MAP_AF (REFCLK_IN, GPIO_AF1); - timer_reset (TIM2); + rcc_periph_reset_pulse (RST_TIM2); timer_set_mode (TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); /* count up with clock*/ timer_slave_set_filter (TIM2, TIM_SMCR_ETF_OFF); /*no filter*/ timer_slave_set_prescaler (TIM2, TIM_SMCR_ETPS_OFF); /*no prescaler */ |