remember old steth

1 files changed, 73 insertions, 12 deletions

diff --git a/app/steth.c b/app/steth.c
index ba3aa72..d7eea7e 100644
--- a/app/steth.c
+++ b/app/steth.c
@@ -34,7 +34,7 @@
 #define NRST_PORT GPIOE
 
 
-#define DESC_SZ 32
+#define DESC_SZ ETH_DES_EXT_SIZE
 #define FRAME_SZ 1516
 
 #define TX_BUFS 4
@@ -42,11 +42,12 @@
 
 #define ETH_BUF_LEN ((TX_BUFS+ RX_BUFS) * (DESC_SZ+FRAME_SZ))
 
+
 static int running;
 
 static uint8_t __attribute__ ((aligned (4))) eth_buf[ETH_BUF_LEN];
 
-static uint8_t sa[ETHARP_HWADDR_LEN] = { 0xc0, 0xf1, 0xee, 0xc0, 0xff, 0xee };
+static uint8_t sa[ETHARP_HWADDR_LEN] = { 0xc0, 0xf1, 0xee, 0xc0, 0xff, 0xdd };
 
 extern uint32_t TxBD;
 extern uint32_t RxBD;
@@ -92,10 +93,12 @@ steth_tx (struct netif *netif, struct pbuf *p)
 
 #endif
 
+#if 0
   {
     static int tx_cnt = 0;
     printf ("TX %d\r\n", tx_cnt++);
   }
+#endif
 
   return ERR_OK;
 }
@@ -106,6 +109,7 @@ steth_rx (void)
   //err_t err;
   struct pbuf *p;
   uint32_t len;
+
 #if 0
   struct pbuf *q;
   static uint8_t rx_buf[FRAME_SZ];
@@ -151,10 +155,12 @@ steth_rx (void)
 
   //      usart6_write (".", 1, 0);
 
+#if 0
   {
     static int rx_cnt = 0;
     printf ("RX %d\r\n", rx_cnt++);
   }
+#endif
 
 
   return if0.input (p, &if0);
@@ -179,8 +185,8 @@ eth_isr (void)
 void
 steth_isr (void)
 {
-#if 0
-  //  printf ("eth\r\n");
+#if 1
+    //printf ("eth\r\n");
 
   if (eth_irq_ack_pending (ETH_DMASR_NIS))
     steth_nis();
@@ -228,7 +234,7 @@ steth_lwip_init (struct netif *netif)
 void
 steth_init (void)
 {
-
+unsigned i;
 
   MAP_AF (TXEN, GPIO_AF11);
   MAP_AF (TXD0, GPIO_AF11);
@@ -239,24 +245,35 @@ steth_init (void)
 
   MAP_AF (CRS_DV, GPIO_AF11);
 
-  MAP_AF (MDIO, GPIO_AF11);
-  MAP_AF (MDC, GPIO_AF11);
+  MAP_INPUT_PU(MDC);
+
+  MAP_AF_PU (MDIO, GPIO_AF11);
+  MAP_AF_PU (MDC, GPIO_AF11);
 
   MAP_AF (REF_CLK, GPIO_AF11);
 
   MAP_OUTPUT_PP (NRST);
 
+
+  CLEAR(NRST);
+  delay_ms(1);
   SET (NRST);
 
+TRACE;
+
   /* The switch to RMII has be done with steth under reset, with no clock */
 
+  rcc_periph_clock_enable (RCC_APB2ENR_SYSCFGEN);
+
+  RCC_AHB1RSTR |= RCC_AHB1RSTR_ETHMACRST; /*Assert RESET */
 
+#if 0
   rcc_periph_clock_disable (RCC_ETHMACPTP);
   rcc_periph_clock_disable (RCC_ETHMACRX);
   rcc_periph_clock_disable (RCC_ETHMACTX);
   rcc_periph_clock_disable (RCC_ETHMAC);
+#endif
 
-  RCC_AHB1RSTR |= RCC_AHB1RSTR_ETHMACRST; /*Assert RESET */
   delay_us (1);
 
 #ifndef SYSCFG_PMC_MII_RMII_SEL
@@ -265,6 +282,7 @@ steth_init (void)
 
   SYSCFG_PMC |= SYSCFG_PMC_MII_RMII_SEL;
 
+TRACE;
   RCC_AHB1RSTR &= ~RCC_AHB1RSTR_ETHMACRST; /*De-sssert RESET */
 
 
@@ -273,11 +291,29 @@ steth_init (void)
   rcc_periph_clock_enable (RCC_ETHMACRX);
   rcc_periph_clock_enable (RCC_ETHMACPTP);
 
+  delay_ms (10);
+  ETH_DMABMR|=1;
+  delay_ms (10);
+
+TRACE;
   eth_desc_init (eth_buf, TX_BUFS, RX_BUFS, FRAME_SZ, FRAME_SZ, 1);
+TRACE;
+
+  for (i=0;i<32;++i) {
+	printf("phy:%x %x\r\n",i,eth_smi_read(PHY,i));
+  }
 
   /*MDC = HCLK / 102 (0b100) => 1.6MHz */
+
   eth_init (PHY, 0x4);
+TRACE;
+//  eth_init (PHY, 0x14);
+TRACE;
   eth_enable_checksum_offload();
+TRACE;
+
+  eth_set_mac (sa);
+
 
 
   printf ("Waiting for link\r\n");
@@ -291,18 +327,24 @@ steth_init (void)
 
   switch (phy_link_status (PHY)) {
   case LINK_HD_10M:
+	TRACE;
   case LINK_FD_10M:
+	TRACE;
     ETH_MACCR &= ~ETH_MACCR_FES;
     break;
 
   default:
+	TRACE;
     ;
   }
 
+	printf("phy link status %x\r\n",phy_link_status(PHY));
 
   switch (phy_link_status (PHY)) {
   case LINK_HD_10M:
+	TRACE;
   case LINK_HD_100M:
+	TRACE;
     ETH_MACCR &= ~ETH_MACCR_DM;
     ETH_MACCR |= ETH_MACCR_ROD;
     break;
@@ -313,7 +355,7 @@ steth_init (void)
 
   ETH_MACCR &= ~ETH_MACCR_RD;
 
-  eth_set_mac (sa);
+
 
   nvic_disable_irq (NVIC_ETH_IRQ);
 
@@ -334,21 +376,34 @@ steth_init (void)
 void
 steth_dispatch (void)
 {
-#if 0
+#if 1
   uint32_t d, s;
 #endif
 
   if (!running)
     return;
 
-#if 0
+#if 1
   printf ("Net:\r\n");
   printf (" ETH_MACCR:    %08" PRIx32 "\r\n", ETH_MACCR);
+#if 0
+  printf (" ETH_MACFFR:   %08" PRIx32 "\r\n", ETH_MACFFR);
+  printf (" ETH_MACFCR:   %08" PRIx32 "\r\n", ETH_MACFCR);
   printf (" ETH_MACDBGR:  %08" PRIx32 "\r\n", ETH_MACDBGR);
-  printf (" ETH_DMASR:    %08" PRIx32 "\r\n", ETH_DMASR);
+  printf (" ETH_MACSR:    %08" PRIx32 "\r\n", ETH_MACSR);
+#endif
+  printf (" ETH_DMAOMR:   %08" PRIx32 "\r\n", ETH_DMAOMR);
+  printf (" ETH_DMASR:    %08" PRIx32 " ebs=%x tps=%x rps=%x\r\n", ETH_DMASR, 
+		(ETH_DMASR >>23) & 7 ,
+		(ETH_DMASR >>20) & 7 ,
+		(ETH_DMASR >>17) & 7 );
   printf (" ETH_DMAIER:   %08" PRIx32 "\r\n", ETH_DMAIER);
   printf (" ETH_DMACHTDR: %08" PRIx32 "\r\n", ETH_DMACHTDR);
   printf (" ETH_DMACHRDR: %08" PRIx32 "\r\n", ETH_DMACHRDR);
+  printf (" ETH_DMAOMR:   %08" PRIx32 "\r\n", ETH_DMAOMR);
+  printf (" ETH_DMATDLAR: %08" PRIx32 "\r\n", ETH_DMATDLAR);
+  printf (" ETH_DMARDLAR: %08" PRIx32 "\r\n", ETH_DMARDLAR);
+  printf (" ETH_DMABMR:   %08" PRIx32 "\r\n", ETH_DMABMR);
 
 
   s = d = RxBD;
@@ -365,7 +420,13 @@ steth_dispatch (void)
 
 #endif
 
+{
+int i;
+for (i=0;i<1000;++i) {
+delay_ms(1);
   steth_isr();
+}
 
 }
+}