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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2016 Rohan Murch <rohan.murch@gmail.com>
* Copyright (C) 2016 Hans Ulli Kroll <ulli.kroll@googlemail.com>
* Copyright (C) 2017 James McKenzie <openwrt@madingley.org>
*/
#include "mt7620a.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/mtd/partitions/uimage.h>
/ {
compatible = "edimax,br-6478ac-v2", "ralink,mt7620a-soc";
model = "Edimax BR-6478AC v2";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
keys {
compatible = "gpio-keys";
reset_wps {
label = "reset_wps";
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led_power: power {
label = "white:power";
gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
};
internet {
label = "blue:internet";
gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
};
wlan {
label = "blue:wlan";
gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
};
usb {
label = "blue:usb";
gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
trigger-sources = <&ohci_port1>, <&ehci_port1>;
linux,default-trigger = "usbport";
};
};
gpio_export {
compatible = "gpio-export";
#size-cells = <0>;
usb-power {
gpio-export,name="usb-power";
gpio-export,output=<1>;
gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
};
};
};
&gpio2 {
status = "okay";
};
&spi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x30000>;
read-only;
};
partition@30000 {
label = "u-boot-env";
reg = <0x30000 0x10000>;
read-only;
};
factory: partition@40000 {
label = "factory";
reg = <0x40000 0x10000>;
read-only;
};
partition@50000 {
label = "cimage";
reg = <0x50000 0x20000>;
read-only;
};
partition@70000 {
compatible = "openwrt,uimage", "denx,uimage";
openwrt,offset = <FW_EDIMAX_OFFSET>;
openwrt,partition-magic = <FW_MAGIC_EDIMAX>;
label = "firmware";
reg = <0x00070000 0x00790000>;
};
};
};
};
&state_default {
gpio {
groups = "i2c", "uartf", "nd_sd";
function = "gpio";
};
};
ðernet {
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
nvmem-cells = <&macaddr_factory_4>;
nvmem-cell-names = "mac-address";
mediatek,portmap = "wllll";
port@5 {
status = "okay";
mediatek,fixed-link = <1000 1 1 1>;
phy-mode = "rgmii";
};
mdio-bus {
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
phy-mode = "rgmii";
};
phy1: ethernet-phy@1 {
reg = <1>;
phy-mode = "rgmii";
};
phy2: ethernet-phy@2 {
reg = <2>;
phy-mode = "rgmii";
};
phy3: ethernet-phy@3 {
reg = <3>;
phy-mode = "rgmii";
};
phy4: ethernet-phy@4 {
reg = <4>;
phy-mode = "rgmii";
};
phy1f: ethernet-phy@1f {
reg = <0x1f>;
phy-mode = "rgmii";
};
};
};
&gsw {
mediatek,ephy-base = /bits/ 8 <12>;
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};
&pcie {
status = "okay";
};
&pcie0 {
wifi@0,0 {
reg = <0x0000 0 0 0 0>;
mediatek,mtd-eeprom = <&factory 0x8000>;
mediatek,2ghz = <0>;
};
};
&ehci {
status = "okay";
};
&ohci {
status = "okay";
};
&factory {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_factory_4: macaddr@4 {
reg = <0x4 0x6>;
};
};
|
