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From 9e7eb0ea442ecb1c3fe443289e288694f10c5148 Mon Sep 17 00:00:00 2001
From: Miquel Raynal <miquel.raynal@bootlin.com>
Date: Thu, 27 Jan 2022 10:18:01 +0100
Subject: [PATCH 07/15] spi: spi-mem: Add an ecc parameter to the spi_mem_op
structure
Soon the SPI-NAND core will need a way to request a SPI controller to
enable ECC support for a given operation. This is because of the
pipelined integration of certain ECC engines, which are directly managed
by the SPI controller itself.
Introduce a spi_mem_op additional field for this purpose: ecc.
So far this field is left unset and checked to be false by all
the SPI controller drivers in their ->supports_op() hook, as they all
call spi_mem_default_supports_op().
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-7-miquel.raynal@bootlin.com
(cherry picked from commit a433c2cbd75ab76f277364f44e76f32c7df306e7)
---
drivers/spi/spi-mem.c | 5 +++++
include/linux/spi/spi-mem.h | 4 ++++
2 files changed, 9 insertions(+)
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -178,6 +178,11 @@ bool spi_mem_default_supports_op(struct
return false;
}
+ if (op->data.ecc) {
+ if (!spi_mem_controller_is_capable(ctlr, ecc))
+ return false;
+ }
+
return spi_mem_check_buswidth(mem, op);
}
EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
--- a/include/linux/spi/spi-mem.h
+++ b/include/linux/spi/spi-mem.h
@@ -89,6 +89,7 @@ enum spi_mem_data_dir {
* @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not
* @data.buswidth: number of IO lanes used to send/receive the data
* @data.dtr: whether the data should be sent in DTR mode or not
+ * @data.ecc: whether error correction is required or not
* @data.dir: direction of the transfer
* @data.nbytes: number of data bytes to send/receive. Can be zero if the
* operation does not involve transferring data
@@ -119,6 +120,7 @@ struct spi_mem_op {
struct {
u8 buswidth;
u8 dtr : 1;
+ u8 ecc : 1;
enum spi_mem_data_dir dir;
unsigned int nbytes;
union {
@@ -288,9 +290,11 @@ struct spi_controller_mem_ops {
/**
* struct spi_controller_mem_caps - SPI memory controller capabilities
* @dtr: Supports DTR operations
+ * @ecc: Supports operations with error correction
*/
struct spi_controller_mem_caps {
bool dtr;
+ bool ecc;
};
#define spi_mem_controller_is_capable(ctlr, cap) \
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