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From d408e9c29dd580cb94e39da2b0eef81061d22061 Mon Sep 17 00:00:00 2001
From: Ran Wang <ran.wang_1@nxp.com>
Date: Thu, 19 Dec 2019 17:02:36 +0800
Subject: [PATCH] LF-387-1 Revert "usb: dwc3: Add cache type configuration
support"
This reverts commit ebceaf435cc96892d22b334b2a6517374c0d6a6e.
Will use next version patch to replace this.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
drivers/usb/dwc3/core.c | 61 +++++--------------------------------------------
drivers/usb/dwc3/core.h | 15 ------------
2 files changed, 6 insertions(+), 70 deletions(-)
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -919,54 +919,6 @@ static void dwc3_set_power_down_clk_scal
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
}
-#ifdef CONFIG_OF
-struct dwc3_cache_type {
- u8 transfer_type_datard;
- u8 transfer_type_descrd;
- u8 transfer_type_datawr;
- u8 transfer_type_descwr;
-};
-
-static const struct dwc3_cache_type layerscape_dwc3_cache_type = {
- .transfer_type_datard = 2,
- .transfer_type_descrd = 2,
- .transfer_type_datawr = 2,
- .transfer_type_descwr = 2,
-};
-
-/**
- * dwc3_set_cache_type - Configure cache type registers
- * @dwc: Pointer to our controller context structure
- */
-static void dwc3_set_cache_type(struct dwc3 *dwc)
-{
- u32 tmp, reg;
- const struct dwc3_cache_type *cache_type =
- device_get_match_data(dwc->dev);
-
- if (cache_type) {
- reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
- tmp = reg;
-
- reg &= ~DWC3_GSBUSCFG0_DATARD(~0);
- reg |= DWC3_GSBUSCFG0_DATARD(cache_type->transfer_type_datard);
-
- reg &= ~DWC3_GSBUSCFG0_DESCRD(~0);
- reg |= DWC3_GSBUSCFG0_DESCRD(cache_type->transfer_type_descrd);
-
- reg &= ~DWC3_GSBUSCFG0_DATAWR(~0);
- reg |= DWC3_GSBUSCFG0_DATAWR(cache_type->transfer_type_datawr);
-
- reg &= ~DWC3_GSBUSCFG0_DESCWR(~0);
- reg |= DWC3_GSBUSCFG0_DESCWR(cache_type->transfer_type_descwr);
-
- if (tmp != reg)
- dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
- }
-}
-#endif
-
-
/**
* dwc3_core_init - Low-level initialization of DWC3 Core
* @dwc: Pointer to our controller context structure
@@ -1027,10 +979,6 @@ static int dwc3_core_init(struct dwc3 *d
dwc3_set_incr_burst_type(dwc);
-#ifdef CONFIG_OF
- dwc3_set_cache_type(dwc);
-#endif
-
usb_phy_set_suspend(dwc->usb2_phy, 0);
usb_phy_set_suspend(dwc->usb3_phy, 0);
ret = phy_power_on(dwc->usb2_generic_phy);
@@ -1984,9 +1932,12 @@ static const struct dev_pm_ops dwc3_dev_
#ifdef CONFIG_OF
static const struct of_device_id of_dwc3_match[] = {
- { .compatible = "fsl,layerscape-dwc3", .data = &layerscape_dwc3_cache_type, },
- { .compatible = "snps,dwc3" },
- { .compatible = "synopsys,dwc3" },
+ {
+ .compatible = "snps,dwc3"
+ },
+ {
+ .compatible = "synopsys,dwc3"
+ },
{ },
};
MODULE_DEVICE_TABLE(of, of_dwc3_match);
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -167,21 +167,6 @@
/* Bit fields */
/* Global SoC Bus Configuration INCRx Register 0 */
-#ifdef CONFIG_OF
-#define DWC3_GSBUSCFG0_DATARD_SHIFT 28
-#define DWC3_GSBUSCFG0_DATARD(n) (((n) & 0xf) \
- << DWC3_GSBUSCFG0_DATARD_SHIFT)
-#define DWC3_GSBUSCFG0_DESCRD_SHIFT 24
-#define DWC3_GSBUSCFG0_DESCRD(n) (((n) & 0xf) \
- << DWC3_GSBUSCFG0_DESCRD_SHIFT)
-#define DWC3_GSBUSCFG0_DATAWR_SHIFT 20
-#define DWC3_GSBUSCFG0_DATAWR(n) (((n) & 0xf) \
- << DWC3_GSBUSCFG0_DATAWR_SHIFT)
-#define DWC3_GSBUSCFG0_DESCWR_SHIFT 16
-#define DWC3_GSBUSCFG0_DESCWR(n) (((n) & 0xf) \
- << DWC3_GSBUSCFG0_DESCWR_SHIFT)
-#endif
-
#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
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