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From 8079cfba4c7b8cae900c27104b4512fa5ed1f021 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
Date: Wed, 17 Jun 2020 12:50:37 +0200
Subject: [PATCH 5/9] mips: bmips: dts: add BCM6358 reset controller support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
BCM6358 SoCs have a reset controller for certain components.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
arch/mips/boot/dts/brcm/bcm6358.dtsi | 6 ++++++
include/dt-bindings/reset/bcm6358-reset.h | 15 +++++++++++++++
2 files changed, 21 insertions(+)
create mode 100644 include/dt-bindings/reset/bcm6358-reset.h
--- a/arch/mips/boot/dts/brcm/bcm6358.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm6358.dtsi
@@ -82,6 +82,12 @@
interrupts = <2>, <3>;
};
+ periph_rst: reset-controller@fffe0034 {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0xfffe0034 0x4>;
+ #reset-cells = <1>;
+ };
+
leds0: led-controller@fffe00d0 {
#address-cells = <1>;
#size-cells = <0>;
--- /dev/null
+++ b/include/dt-bindings/reset/bcm6358-reset.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6358_H
+#define __DT_BINDINGS_RESET_BCM6358_H
+
+#define BCM6358_RST_SPI 0
+#define BCM6358_RST_ENET 2
+#define BCM6358_RST_MPI 3
+#define BCM6358_RST_EPHY 6
+#define BCM6358_RST_SAR 7
+#define BCM6358_RST_USBH 12
+#define BCM6358_RST_PCM 13
+#define BCM6358_RST_ADSL 14
+
+#endif /* __DT_BINDINGS_RESET_BCM6358_H */
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