aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/bcm63xx/patches-5.10/320-irqchip-add-support-for-bcm6345-style-periphery-irq-.patch
blob: a067c0202e4d53af5a1480bf78f9dde63fe415a3 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
From 301744ecbeece89ab3a9d6beef7802fa22598f00 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Sun, 30 Nov 2014 14:53:12 +0100
Subject: [PATCH 1/5] irqchip: add support for bcm6345-style periphery irq
 controller

Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
 .../brcm,bcm6345-periph-intc.txt                   |   50 +++
 drivers/irqchip/Kconfig                            |    4 +
 drivers/irqchip/Makefile                           |    1 +
 drivers/irqchip/irq-bcm6345-periph.c               |  339 ++++++++++++++++++++
 include/linux/irqchip/irq-bcm6345-periph.h         |   16 +
 5 files changed, 410 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-periph-intc.txt
 create mode 100644 drivers/irqchip/irq-bcm6345-periph.c
 create mode 100644 include/linux/irqchip/irq-bcm6345-periph.h

--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-periph-intc.txt
@@ -0,0 +1,50 @@
+Broadcom BCM6345 Level 1 periphery interrupt controller
+
+This block is a  interrupt controller that is typically connected directly
+to one of the HW INT lines on each CPU.  Every BCM63XX xDSL chip since
+BCM6345 has contained this hardware.
+
+Key elements of the hardware design include:
+
+- 32, 64, or 128 incoming level IRQ lines
+
+- All onchip peripherals are wired directly to an L2 input
+
+- A separate instance of the register set for each CPU, allowing individual
+  peripheral IRQs to be routed to any CPU
+
+- No atomic mask/unmask operations
+
+- No polarity/level/edge settings
+
+- No FIFO or priority encoder logic; software is expected to read all
+  1-4 status words to determine which IRQs are pending
+
+Required properties:
+
+- compatible: Should be "brcm,bcm6345-periph-intc".
+- reg: Specifies the base physical address and size of the registers.
+  Multiple register addresses may be specified, and must match the amount of
+  parent interrupts.
+- interrupt-controller: Identifies the node as an interrupt controller.
+- #interrupt-cells: Specifies the number of cells needed to encode an interrupt
+  source, should be 1.
+- interrupt-parent: Specifies the phandle to the parent interrupt controller
+  this one is cascaded from.
+- interrupts: Specifies the interrupt line(s) in the interrupt-parent controller
+  node, valid values depend on the type of parent interrupt controller.
+  Multiple lines are used to route interrupts to different cpus, with the first
+  assumed to be for the boot CPU.
+
+Example:
+
+periph_intc: interrupt-controller@f0406800 {
+	compatible = "brcm,bcm6345-periph-intc";
+	reg = <0x10000020 0x10>, <0x10000030 0x10>;
+
+	interrupt-controller;
+	#interrupt-cells = <1>;
+
+	interrupt-parent = <&cpu_intc>;
+	interrupts = <2>, <3>;
+};
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -145,6 +145,10 @@ config DAVINCI_CP_INTC
 	select GENERIC_IRQ_CHIP
 	select IRQ_DOMAIN
 
+config BCM6345_PERIPH_IRQ
+	bool
+	select IRQ_DOMAIN
+
 config DW_APB_ICTL
 	bool
 	select GENERIC_IRQ_CHIP
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_ARCH_LPC32XX)		+= irq-lpc32
 obj-$(CONFIG_ARCH_MMP)			+= irq-mmp.o
 obj-$(CONFIG_IRQ_MXS)			+= irq-mxs.o
 obj-$(CONFIG_ARCH_TEGRA)		+= irq-tegra.o
+obj-$(CONFIG_BCM6345_PERIPH_IRQ)	+= irq-bcm6345-periph.o
 obj-$(CONFIG_DW_APB_ICTL)		+= irq-dw-apb-ictl.o
 obj-$(CONFIG_CLPS711X_IRQCHIP)		+= irq-clps711x.o
 obj-$(CONFIG_OMPIC)			+= irq-ompic.o
--- /dev/null
+++ b/drivers/irqchip/irq-bcm6345-periph.c
@@ -0,0 +1,339 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
+ */
+
+#include <linux/ioport.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqchip/irq-bcm6345-periph.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#ifdef CONFIG_BCM63XX
+#include <asm/mach-bcm63xx/bcm63xx_irq.h>
+
+#define VIRQ_BASE	IRQ_INTERNAL_BASE
+#else
+#define VIRQ_BASE	0
+#endif
+
+#define MAX_WORDS	4
+#define MAX_PARENT_IRQS	2
+#define IRQS_PER_WORD	32
+
+struct intc_block {
+	int parent_irq;
+	void __iomem *base;
+	void __iomem *en_reg[MAX_WORDS];
+	void __iomem *status_reg[MAX_WORDS];
+	u32 mask_cache[MAX_WORDS];
+};
+
+struct intc_data {
+	struct irq_chip chip;
+	struct intc_block block[MAX_PARENT_IRQS];
+
+	int num_words;
+
+	struct irq_domain *domain;
+	raw_spinlock_t lock;
+};
+
+static void bcm6345_periph_irq_handle(struct irq_desc *desc)
+{
+	struct intc_data *data = irq_desc_get_handler_data(desc);
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	struct intc_block *block;
+	unsigned int irq = irq_desc_get_irq(desc);
+	unsigned int idx;
+
+	chained_irq_enter(chip, desc);
+
+	for (idx = 0; idx < MAX_PARENT_IRQS; idx++)
+		if (irq == data->block[idx].parent_irq)
+			block = &data->block[idx];
+
+	for (idx = 0; idx < data->num_words; idx++) {
+		int base = idx * IRQS_PER_WORD;
+		unsigned long pending;
+		int hw_irq;
+
+		raw_spin_lock(&data->lock);
+		pending = __raw_readl(block->en_reg[idx]) &
+			  __raw_readl(block->status_reg[idx]);
+		raw_spin_unlock(&data->lock);
+
+		for_each_set_bit(hw_irq, &pending, IRQS_PER_WORD) {
+			int virq;
+
+			virq  = irq_find_mapping(data->domain, base + hw_irq);
+			generic_handle_irq(virq);
+		}
+	}
+
+	chained_irq_exit(chip, desc);
+}
+
+static void __bcm6345_periph_enable(struct intc_block *block, int reg, int bit,
+				    bool enable)
+{
+	u32 val;
+
+	val = __raw_readl(block->en_reg[reg]);
+	if (enable)
+		val |= BIT(bit);
+	else
+		val &= ~BIT(bit);
+	__raw_writel(val, block->en_reg[reg]);
+}
+
+static void bcm6345_periph_irq_mask(struct irq_data *data)
+{
+	unsigned int i, reg, bit;
+	struct intc_data *priv = data->domain->host_data;
+	irq_hw_number_t hwirq = irqd_to_hwirq(data);
+
+	reg = hwirq / IRQS_PER_WORD;
+	bit = hwirq % IRQS_PER_WORD;
+
+	raw_spin_lock(&priv->lock);
+	for (i = 0; i < MAX_PARENT_IRQS; i++) {
+		struct intc_block *block = &priv->block[i];
+
+		if (!block->parent_irq)
+			break;
+
+		__bcm6345_periph_enable(block, reg, bit, false);
+	}
+	raw_spin_unlock(&priv->lock);
+}
+
+static void bcm6345_periph_irq_unmask(struct irq_data *data)
+{
+	struct intc_data *priv = data->domain->host_data;
+	irq_hw_number_t hwirq = irqd_to_hwirq(data);
+	unsigned int i, reg, bit;
+
+	reg = hwirq / IRQS_PER_WORD;
+	bit = hwirq % IRQS_PER_WORD;
+
+	raw_spin_lock(&priv->lock);
+	for (i = 0; i < MAX_PARENT_IRQS; i++) {
+		struct intc_block *block = &priv->block[i];
+
+		if (!block->parent_irq)
+			break;
+
+		if (block->mask_cache[reg] & BIT(bit))
+			__bcm6345_periph_enable(block, reg, bit, true);
+		else
+			__bcm6345_periph_enable(block, reg, bit, false);
+	}
+	raw_spin_unlock(&priv->lock);
+}
+
+#ifdef CONFIG_SMP
+static int bcm6345_periph_set_affinity(struct irq_data *data,
+				       const struct cpumask *mask, bool force)
+{
+	irq_hw_number_t hwirq = irqd_to_hwirq(data);
+	struct intc_data *priv = data->domain->host_data;
+	unsigned int i, reg, bit;
+	unsigned long flags;
+	bool enabled;
+	int cpu;
+
+	reg = hwirq / IRQS_PER_WORD;
+	bit = hwirq % IRQS_PER_WORD;
+
+	/* we could route to more than one cpu, but performance
+	   suffers, so fix it to one.
+	 */
+	cpu = cpumask_any_and(mask, cpu_online_mask);
+	if (cpu >= nr_cpu_ids)
+		return -EINVAL;
+
+	if (cpu >= MAX_PARENT_IRQS)
+		return -EINVAL;
+
+	if (!priv->block[cpu].parent_irq)
+		return -EINVAL;
+
+	raw_spin_lock_irqsave(&priv->lock, flags);
+	enabled = !irqd_irq_masked(data);
+	for (i = 0; i < MAX_PARENT_IRQS; i++) {
+		struct intc_block *block = &priv->block[i];
+
+		if (!block->parent_irq)
+			break;
+
+		if (i == cpu) {
+			block->mask_cache[reg] |= BIT(bit);
+			__bcm6345_periph_enable(block, reg, bit, enabled);
+		} else {
+			block->mask_cache[reg] &= ~BIT(bit);
+			__bcm6345_periph_enable(block, reg, bit, false);
+		}
+	}
+	raw_spin_unlock_irqrestore(&priv->lock, flags);
+
+	return 0;
+}
+#endif
+
+static int bcm6345_periph_map(struct irq_domain *d, unsigned int irq,
+			      irq_hw_number_t hw)
+{
+	struct intc_data *priv = d->host_data;
+
+	irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq);
+
+	return 0;
+}
+
+static const struct irq_domain_ops bcm6345_periph_domain_ops = {
+	.xlate = irq_domain_xlate_onecell,
+	.map = bcm6345_periph_map,
+};
+
+static int __init __bcm6345_periph_intc_init(struct device_node *node,
+					     int num_blocks, int *irq,
+					     void __iomem **base, int num_words)
+{
+	struct intc_data *data;
+	unsigned int i, w, status_offset;
+
+	data = kzalloc(sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	raw_spin_lock_init(&data->lock);
+
+	status_offset = num_words * sizeof(u32);
+
+	for (i = 0; i < num_blocks; i++) {
+		struct intc_block *block = &data->block[i];
+
+		block->parent_irq = irq[i];
+		block->base = base[i];
+
+		for (w = 0; w < num_words; w++) {
+			int word_offset = sizeof(u32) * ((num_words - w) - 1);
+
+			block->en_reg[w] = base[i] + word_offset;
+			block->status_reg[w] = base[i] + status_offset;
+			block->status_reg[w] += word_offset;
+
+			/* route all interrupts to line 0 by default */
+			if (i == 0)
+				block->mask_cache[w] = 0xffffffff;
+		}
+
+		irq_set_handler_data(block->parent_irq, data);
+		irq_set_chained_handler(block->parent_irq,
+					bcm6345_periph_irq_handle);
+	}
+
+	data->num_words = num_words;
+
+	data->chip.name = "bcm6345-periph-intc";
+	data->chip.irq_mask = bcm6345_periph_irq_mask;
+	data->chip.irq_unmask = bcm6345_periph_irq_unmask;
+
+#ifdef CONFIG_SMP
+	if (num_blocks > 1)
+		data->chip.irq_set_affinity = bcm6345_periph_set_affinity;
+#endif
+
+	data->domain = irq_domain_add_simple(node, IRQS_PER_WORD * num_words,
+					     VIRQ_BASE,
+					     &bcm6345_periph_domain_ops, data);
+	if (!data->domain) {
+		kfree(data);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+void __init bcm6345_periph_intc_init(int num_blocks, int *irq,
+				     void __iomem **base, int num_words)
+{
+	__bcm6345_periph_intc_init(NULL, num_blocks, irq, base, num_words);
+}
+
+#ifdef CONFIG_OF
+static int __init bcm6345_periph_of_init(struct device_node *node,
+					 struct device_node *parent)
+{
+	struct resource res;
+	int num_irqs, ret = -EINVAL;
+	int irqs[MAX_PARENT_IRQS] = { 0 };
+	void __iomem *bases[MAX_PARENT_IRQS] = { NULL };
+	int words = 0;
+	int i;
+
+	num_irqs = of_irq_count(node);
+
+	if (num_irqs < 1 || num_irqs > MAX_PARENT_IRQS)
+		return -EINVAL;
+
+	for (i = 0; i < num_irqs; i++) {
+		resource_size_t size;
+
+		irqs[i] = irq_of_parse_and_map(node, i);
+		if (!irqs[i])
+			goto out_unmap;
+
+		if (of_address_to_resource(node, i, &res))
+			goto out_unmap;
+
+		size = resource_size(&res);
+		switch (size) {
+		case 8:
+		case 16:
+		case 32:
+			size = size / 8;
+			break;
+		default:
+			goto out_unmap;
+		}
+
+		if (words && words != size) {
+			ret = -EINVAL;
+			goto out_unmap;
+		}
+		words = size;
+
+		bases[i] = of_iomap(node, i);
+		if (!bases[i]) {
+			ret = -ENOMEM;
+			goto out_unmap;
+		}
+	}
+
+	ret = __bcm6345_periph_intc_init(node, num_irqs, irqs, bases, words);
+	if (!ret)
+		return 0;
+
+out_unmap:
+	for (i = 0; i < num_irqs; i++) {
+		iounmap(bases[i]);
+		irq_dispose_mapping(irqs[i]);
+	}
+
+	return ret;
+}
+
+IRQCHIP_DECLARE(bcm6345_periph_intc, "brcm,bcm6345-l1-intc",
+		bcm6345_periph_of_init);
+#endif
--- /dev/null
+++ b/include/linux/irqchip/irq-bcm6345-periph.h
@@ -0,0 +1,16 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
+ * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
+ */
+
+#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H
+#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H
+
+void bcm6345_periph_intc_init(int num_blocks, int *irq, void __iomem **base,
+			      int num_words);
+
+#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H */