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From 25402f4978434949e5ea550c9b1b4a192e95fd83 Mon Sep 17 00:00:00 2001
From: Dom Cobley <popcornmix@gmail.com>
Date: Thu, 7 May 2020 18:16:07 +0100
Subject: [PATCH] vc4_hdmi: Fix up CEC registers
Fix an incorrect register address, add a
missing one and reorder into address order
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
---
drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
--- a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
@@ -33,11 +33,12 @@ enum vc4_hdmi_field {
HDMI_CEC_CNTRL_3,
HDMI_CEC_CNTRL_4,
HDMI_CEC_CNTRL_5,
+ HDMI_CEC_CPU_STATUS,
+ HDMI_CEC_CPU_SET,
HDMI_CEC_CPU_CLEAR,
- HDMI_CEC_CPU_MASK_CLEAR,
- HDMI_CEC_CPU_MASK_SET,
HDMI_CEC_CPU_MASK_STATUS,
- HDMI_CEC_CPU_STATUS,
+ HDMI_CEC_CPU_MASK_SET,
+ HDMI_CEC_CPU_MASK_CLEAR,
/*
* Transmit data, first byte is low byte of the 32-bit reg.
@@ -205,9 +206,10 @@ static const struct vc4_hdmi_register vc
VC4_HDMI_REG(HDMI_TX_PHY_RESET_CTL, 0x02c0),
VC4_HDMI_REG(HDMI_TX_PHY_CTL_0, 0x02c4),
VC4_HDMI_REG(HDMI_CEC_CPU_STATUS, 0x0340),
+ VC4_HDMI_REG(HDMI_CEC_CPU_SET, 0x0344),
VC4_HDMI_REG(HDMI_CEC_CPU_CLEAR, 0x0348),
VC4_HDMI_REG(HDMI_CEC_CPU_MASK_STATUS, 0x034c),
- VC4_HDMI_REG(HDMI_CEC_CPU_MASK_SET, 0x034c),
+ VC4_HDMI_REG(HDMI_CEC_CPU_MASK_SET, 0x0350),
VC4_HDMI_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0354),
VC4_HDMI_REG(HDMI_RAM_PACKET_START, 0x0400),
};
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