blob: 6c839a24744d4e24fbbd56bf9a1fa9a120c2d2fc (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
|
/*
* ADM8668 minimal clock support
*
* Copyright (C) 2012, Florian Fainelli <florian@openwrt.org>
*
* Licensed under the terms of the GPLv2
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <adm8668.h>
struct clk {
unsigned long rate;
};
static struct clk uart_clk = {
.rate = ADM8668_UARTCLK_FREQ,
};
static struct clk sys_clk;
struct clk *clk_get(struct device *dev, const char *id)
{
const char *lookup = id;
if (dev)
lookup = dev_name(dev);
if (!strcmp(lookup, "apb:uart0"))
return &uart_clk;
if (!strcmp(lookup, "sys"))
return &sys_clk;
return ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL(clk_get);
int clk_enable(struct clk *clk)
{
return 0;
}
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
return clk->rate;
}
EXPORT_SYMBOL(clk_get_rate);
void clk_put(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_put);
void __init adm8668_init_clocks(void)
{
u32 adj;
/* adjustable clock selection
* CR3 bit 14~11, 0000 -> 175MHz, 0001 -> 180MHz, etc...
*/
adj = (ADM8668_CONFIG_REG(ADM8668_CR3) >> 11) & 0xf;
sys_clk.rate = SYS_CLOCK + adj * 5000000;
pr_info("ADM8668 CPU clock: %lu MHz\n", sys_clk.rate / 1000000);
}
|
