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-rwxr-xr-x	abs2rel.pl	330	log stats plain
-rwxr-xr-x	arm-magic.sh	1819	log stats plain
-rwxr-xr-x	brcmImage.pl	3843	log stats plain
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-rwxr-xr-x	dl_cleanup.py	5871	log stats plain
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-rwxr-xr-x	gen-dependencies.sh	653	log stats plain
-rwxr-xr-x	getver.sh	686	log stats plain
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-rw-r--r--	om2p-fwupgradecfg-gen.sh	1548	log stats plain
-rwxr-xr-x	pad_image	2436	log stats plain
-rwxr-xr-x	patch-kernel.sh	1391	log stats plain
-rwxr-xr-x	patch-specs.sh	1780	log stats plain
-rwxr-xr-x	relink-lib.sh	403	log stats plain
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-rwxr-xr-x	timestamp.pl	1371	log stats plain
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"p">))); #endif } void eeprom_read_block(void *buf, const void *addr, size_t len) { init_spi_if_required(); //------------------------------------------------- // Wait for the write-in-progress bit to be cleared bool res = spi_eeprom_start(); if (!res) { dprint("failed to start SPI for WIP check\n"); memset(buf, 0, len); return; } spi_status_t response = spi_eeprom_wait_while_busy(EXTERNAL_EEPROM_SPI_TIMEOUT); spi_stop(); if (response == SPI_STATUS_TIMEOUT) { dprint("SPI timeout for WIP check\n"); memset(buf, 0, len); return; } //------------------------------------------------- // Perform read res = spi_eeprom_start(); if (!res) { dprint("failed to start SPI for read\n"); memset(buf, 0, len); return; } spi_write(CMD_READ); spi_eeprom_transmit_address((uintptr_t)addr); spi_receive(buf, len); #ifdef DEBUG_EEPROM_OUTPUT dprintf("[EEPROM R] 0x%08lX: ", ((uint32_t)(uintptr_t)addr)); for (size_t i = 0; i < len; ++i) { dprintf(" %02X", (int)(((uint8_t *)buf)[i])); } dprintf("\n"); #endif // DEBUG_EEPROM_OUTPUT spi_stop(); } void eeprom_write_block(const void *buf, void *addr, size_t len) { init_spi_if_required(); bool res; uint8_t * read_buf = (uint8_t *)buf; uintptr_t target_addr = (uintptr_t)addr; while (len > 0) { uintptr_t page_offset = target_addr % EXTERNAL_EEPROM_PAGE_SIZE; int write_length = EXTERNAL_EEPROM_PAGE_SIZE - page_offset; if (write_length > len) { write_length = len; } //------------------------------------------------- // Wait for the write-in-progress bit to be cleared res = spi_eeprom_start(); if (!res) { dprint("failed to start SPI for WIP check\n"); return; } spi_status_t response = spi_eeprom_wait_while_busy(EXTERNAL_EEPROM_SPI_TIMEOUT); spi_stop(); if (response == SPI_STATUS_TIMEOUT) { dprint("SPI timeout for WIP check\n"); return; } //------------------------------------------------- // Enable writes res = spi_eeprom_start(); if (!res) { dprint("failed to start SPI for write-enable\n"); return; } spi_write(CMD_WREN); spi_stop(); //------------------------------------------------- // Perform the write res = spi_eeprom_start(); if (!res) { dprint("failed to start SPI for write\n"); return; } #ifdef DEBUG_EEPROM_OUTPUT dprintf("[EEPROM W] 0x%08lX: ", ((uint32_t)(uintptr_t)target_addr)); for (size_t i = 0; i < write_length; i++) { dprintf(" %02X", (int)(uint8_t)(read_buf[i])); } dprintf("\n"); #endif // DEBUG_EEPROM_OUTPUT spi_write(CMD_WRITE); spi_eeprom_transmit_address(target_addr); spi_transmit(read_buf, write_length); spi_stop(); read_buf += write_length; target_addr += write_length; len -= write_length; } //------------------------------------------------- // Disable writes res = spi_eeprom_start(); if (!res) { dprint("failed to start SPI for write-disable\n"); return; } spi_write(CMD_WRDI); spi_stop(); }